Floating-body memory cell write

Details Floating-body memory cell write Floating-body memory cell write

2006-06-13

2006-06-13

Le, Vu A. (Department: 2824)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185280

Reexamination Certificate

active

07061806

ABSTRACT:
A system to write to a plurality of memory cells coupled to a word line, each of the plurality of memory cells comprising a transistor having a source, a drain, a body and a gate coupled to the word line. Some embodiments provide biasing of one or more of the plurality of memory cells in saturation to inject charge carriers into the body of the one or more of the plurality of memory cells, and biasing of each of the plurality of memory cells in accumulation to tunnel charge carriers from the body of each of the plurality of memory cells to the gate of each of the plurality of memory cells.

REFERENCES:
patent: 6714436 (2004-03-01), Burnett et al.
patent: 6852524 (2005-02-01), Okamura et al.
patent: 6873539 (2005-03-01), Fazan et al.
Ohsawa, Takashi et al “Memory Design Using One-Transistor Gain Cell on SOI”, ISSCC 2002, Session 9, Dram and Ferroelectric Memories, 9.1, Feb. 5, 2002. 3 pgs.

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