Floating-body dynamic random access memory and method of...

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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C257S402000, C438S149000

Reexamination Certificate

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07098507

ABSTRACT:
A floating-body dynamic random access memory device may include a semiconductor body having a top surface and laterally opposite sidewalls formed on a substrate. A gate dielectric layer may be formed on the top surface of the semiconductor body and on the laterally opposite sidewalls of the semiconductor body. A gate electrode may be formed on the gate dielectric on the top surface of the semiconductor body and adjacent to the gate dielectric on the laterally opposite sidewalls of the semiconductor body. The gate electrode may only partially deplete a region of the semiconductor body, and the partially depleted region may be used as a storage node for logic states.

REFERENCES:
patent: 6303425 (2001-10-01), Maeda et al.
patent: 6919601 (2005-07-01), Inaba
patent: 2004/0036126 (2004-02-01), Chau et al.
patent: 2004/0094807 (2004-05-01), Chau et al.
T. Ohsawa et al, “Memory design using one-transistor gain cell on SOI,” 2002 International Solid-State Circuits Conference, p. 152.
B. Doyle et al, “Tri-gate fully-depleted CMOS transistors: fabrication, design and layout,” 2003 Symposium on VLSI Technology.
David Lammers, “Intel Peers Through 3 Gates at Post-planar-CMOS World,” EETimes, Oct. 2, 2002.
G.A. Brown et al, “Scaling CMOS: materials and devices,” materialstoday, pp. 20-25, Jan. 2004.

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