Flip-flop, integrated circuit, and flip-flop resetting method

Details Flip-flop, integrated circuit, and flip-flop resetting method Flip-flop, integrated circuit, and flip-flop resetting method

2008-07-22

2008-07-22

Tran, Anh Q (Department: 2819)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

Field-effect transistor

C326S033000, C326S098000

Reexamination Certificate

active

07403042

ABSTRACT:
A flip-flop which eliminates a reset wiring to prevent complication of a wiring in an LSI or to increase the number of channels used for a signal wiring, an integrated circuit using the same, and a flip-flop resetting method, are provided. The flip-flop performing a reset operation by detecting a change in a power supply voltage includes a state retaining node that stores a HIGH level voltage or a LOW level voltage, and a reset signal generation circuit that detects a change in a power supply voltage exceeding a predetermined value to generate a reset signal for resetting a data storing state of the state retaining node.

REFERENCES:
patent: 5821787 (1998-10-01), McClintock et al.
patent: 6728158 (2004-04-01), Takahashi et al.
patent: 2003/0147287 (2003-08-01), Lee
patent: 02-100413 (1990-04-01), None

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