Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Reexamination Certificate
2001-10-10
2004-07-27
Lee, Eddie (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified material other than unalloyed aluminum
C257S786000, C257S778000, C257S737000, C257S762000, C257S529000
Reexamination Certificate
active
06768199
ABSTRACT:
This application relies for priority upon Korean Patent Application No.2001-19307, filed on Apr. 11, 2001, the contents of which are herein incorporated by reference in their entirety.
FIELD OF THE INVENTION
The present invention relates to a semiconductor device and method of fabricating the same, and more particularly to a flip chip type semiconductor device and method of fabricating the same.
BACKGROUND OF THE INVENTION
Semiconductor devices are generally sealed through a packaging process to protect them from the external environment. In the package process, a pad of the semiconductor device is connected to a lead of a lead frame by means of a bonding wire. However, there is a limit in improving reliability and electrical characteristics of the semiconductor device. Accordingly, in recent years, a flip chip package process is widely used in the fabrication of high performance semiconductor devices.
FIG. 1
is a cross-sectional view illustrating a conventional method of fabricating a flip chip type semiconductor device. In the drawing, the portions indicated by reference signs “a” and “b” represent pad and fuse areas, respectively.
Referring to
FIG. 1
, an interlayer insulation layer
3
is formed on a surface of a semiconductor substrate
1
. The interlayer insulation layer
3
is then patterned to form via holes (not shown) which pass through a given region thereof Over the whole surface of the substrate
1
on which the via holes are formed, a final interlayer insulation layer
5
is formed. The final interlayer insulation layer
5
is then patterned to form at least one first groove and at least one second groove in the pad and fuse areas a, b, respectively. In the first and second grooves, first and second metal lines
10
a
,
10
b
are formed by means of a damascene process. The second metal line
10
b
corresponds to a fuse. The first and second metal lines
10
a
,
10
b
comprise a copper layer pattern
9
having superior conductivity and electromigration as compared with an aluminum layer, and a diffusion barrier metal layer pattern
7
enclosing side walls and bottoms of the copper layer pattern
9
.
Over the whole surface of the substrate including the first and second metal lines
10
a
,
10
b
, a passivation layer
18
is formed. The passivation layer
18
is formed by depositing a lower silicon nitride layer
13
, an intermediate silicon oxide layer
15
and an upper silicon nitride layer
17
in order. The lower silicon nitride layer
13
functions as a diffusion barrier layer for preventing copper elements in the copper layer pattern
9
from penetrating through the final interlayer insulation layer
5
. Then, the passivation layer
18
is patterned to form a pad contact hole exposing the first metal line
10
a
. Over the whole surface of the substrate over which the pad contact hole is formed, a barrier metal layer and a pad metal layer are sequentially formed. And then, the pad metal layer and the barrier metal layer are continuously patterned to form a pad
24
covering the pad contact hole. The pad
24
comprises a barrier metal layer pattern
21
and a pad metal layer pattern
23
which are sequentially stacked.
Subsequently, the upper silicon nitride layer
17
is patterned to form an opening
27
on the fuse, i.e., the upper part of the second metal line
10
b
. After a polyimide layer
29
is formed over the whole surface of the substrate over which the opening
27
is formed, the polyimide layer
29
is patterned. As a result, a pad opening exposing the pad
24
and a fuse opening
31
exposing the silicon oxide layer
15
on the second metal line
10
b
are formed. On the exposed pad
24
, an under-bump metal layer pattern
33
and a bump
35
are formed.
As described above, according to the conventional method, a back-end process is complicated. Also, since the cooper layer pattern is used as the fuse, it is difficult to cut the fuse using a laser during a repair process.
SUMMARY OF THE INVENTION
Therefore, it is an object of the present invention to provide an improved method of fabricating a flip chip type semiconductor device which can simplify a back-end process and form a fuse with a material that is easy to cut using a laser.
It is another object of the present invention to provide an improved flip chip type semiconductor device which is fabricated by the improved method described above.
These and other objects are provided, according to an aspect of the present invention, by a method of fabricating a flip chip type semiconductor device having pad and fuse areas. The method of the invention comprises forming an interlayer insulation layer and a passivation layer in order on a semiconductor substrate and forming at least one first metal line and at least a pair of second metal lines in the passivation layer. The first metal line is formed in the pad area, and the second metal lines are formed in the fuse area. Over the surface of the substrate including the first and second metal lines, a metal layer is formed. The metal layer is patterned so as to form a pad covering a portion of the first metal line and a fuse covering the pair of the second metal lines and the passivation layer therebetween. Consequently, the fuse is formed of the same material metal layer as the pad, and the pair of second metal lines are electrically interconnected to each other. Subsequently, a polyimide layer is formed over the whole surface of the substrate including the pad and the fuse. The polyimide layer has a pad opening exposing the pad. On the exposed pad, an under-bump metal layer pattern and a bump are formed.
Another aspect of the present invention may be provided by a flip chip type semiconductor device having pad and fuse areas. The flip chip type semiconductor device comprises an interlayer insulation layer formed on a semiconductor substrate and a passivation layer formed on the interlayer insulation layer. In the passivation layer, at least one first metal line and at least a pair of second metal lines are disposed. The first metal line is disposed in the pad area, and the second metal lines are disposed in the fuse area. A given portion of the first metal line is covered with a pad, and the pair of second metal lines adjacent to each other and the passivation layer therebetween are covered with a fuse. The fuse and the pad are formed of the same material layer. A polyimide layer covers the surface of the semiconductor substrate including the pad and fuse. The polyimide layer has a pad opening exposing the pad. On the exposed pad, an under-bump metal layer pattern and a bump are disposed in order.
REFERENCES:
patent: 5985765 (1999-11-01), Hsiao et al.
patent: 6440833 (2002-08-01), Lee et al.
patent: 6451681 (2002-09-01), Greer
patent: 6649997 (2003-11-01), Koike
Ahn Jong-Hyon
Lee Chang-Hun
Yoon Jung-Lim
Lee Eddie
Mills & Onello LLP
Parekh Nitin
Samsung Electronics Co,. Ltd.
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