Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2001-01-08
2003-02-25
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06526540
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates generally to trace routing techniques for integrated circuits. More specifically, but without limitation thereto, the present invention relates to generating a trace library for a flip chip ball grid array package.
Trace libraries for flip chip bump and trace layouts are currently generated manually in a mask level graphics editor. Trace layouts are typically stored in a standard data format for later recall. A trace library generally requires more than two weeks of effort by an experienced computer aided drafting (CAD) designer to build and verify. The process of drawing traces is tedious and error prone, and each of the many traces must follow strict spacing rules. For each new flip chip technology, new trace libraries are required for each bump pitch. For three bump pitches, for example, three trace libraries must be generated. Also, every time any of several other technology dependent parameters (TDP) change, the trace layouts previously drawn must be revisited and new trace libraries generated.
SUMMARY OF THE INVENTION
The present invention advantageously addresses the problems above as well as other problems by providing a method and a computer program for generating and updating trace libraries automatically.
In one embodiment, the invention may be characterized as a method of generating a trace library that includes the steps of receiving as inputs a plurality of technology dependent parameters and a trace template and generating a bump and trace layout from the inputs.
The features and advantages summarized above in addition to other aspects of the present invention will become more apparent from the description, presented in conjunction with the following drawings.
REFERENCES:
patent: 5877833 (1999-03-01), Schraivogel et al.
patent: 6321367 (2001-11-01), Chun et al.
Shenoy et al, “Flip Chip Package Design Optimization”, IEEE, 1999.
Fong Eric
Liang Mike Teh-An
Tran Thinh
Bowers Brandon
Fitch Even Tabin & Flannery
LSI Logic Corporation
Siek Vuthe
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