Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Assembly of plural semiconductive substrates each possessing...
Utility Patent
1998-12-22
2001-01-02
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Assembly of plural semiconductive substrates each possessing...
C438S107000, C438S106000, C438S029000, C438S156000
Utility Patent
active
06168972
ABSTRACT:
FIELD OF THE INVENTION
This invention is generally related to the field of semiconductor device packaging, and more particularly to underfilling processes for flip chip bonding a chip to a substrate.
BACKGROUND OF THE INVENTION
Flip chip bonding is a technique is which connections are made between a semiconductor chip and a header. Typically, bead-like projections (conductive bumps) are deposited as terminals on one face of the chip, which are then registered and bonded with header terminals disposed on a substrate module. The substrate module is commonly comprised of a ceramic material, although there is increasing interest in substrates comprised of other materials, such as plastics.
Flip chip bonding provides many advantages compared with making connections to a ceramic header using wire-bonding techniques. These advantages include a reduction in interconnection lengths; a smaller package footprint; and a lower package profile compared with conventional wire bonding techniques. Additionally, flip chip bonding techniques may permit an increased number of input/output interconnections to a chip. The flip chip bonding technique has the potential to provide connections distributed throughout the entire area of a chip with the potential number of connections for a fixed chip size being primarily limited by how densely separate solder connections can be reliably made to contact pads on the chip. In contrast, the number of input/output connections possible with conventional wire bonding is limited by how closely wire bonds can be made along the periphery of a chip.
One common flip-chip bonding technique is termed the “ball grid array” mounting technique, in which a pattern of closely positioned solder balls are used to provide a flip-chip connection between the chip and a ceramic substrate module. However a major concern with the ball grid array package is solder joint reliability.
As is well known in mechanical engineering, a statically determinate member (one that is free to move) comprised of a homogenous isotropic material experiences a differential increase in length as a result of a differential increase in temperature in accordance with the mathematical relationship: &dgr;
T
=&agr;&Dgr;TL, where &dgr;
T
is the differential increase in length of the member, &agr; is the linear coefficient of thermal expansion, &Dgr;T is the differential change in temperature of the member, and L is the original length of the member. However, a statically indeterminate member whose thermal displacements are constrained, does not change in length but instead becomes thermally stressed. It is well known that when two materials having a large mismatch between their thermal coefficients of expansion (TCE) are rigidly joined together, stresses and strains may develop in the combined structure.
This is important because there is a substantial difference in the TCE of various components of a flip-chip bonding process. For example, the TCE of a semiconductor chip is typically 2.5 parts per million per degree Celsius (ppm/°C.). The TCE of a ceramic substrate module is typically in the range of 10-30 ppm/°C. Although the TCE of common solders varies somewhat with solder composition, common solder materials have a TCE in the range of about 20-25 ppm/°C.
The large difference in TCE between the different components may cause substantial thermal stress. For example, an unattached ceramic module with a TCE of 25 ppm/°C. and a length of 2 centimeter (cm) would expand by 30 microns for a 60° C. temperature rise. By way of comparison, an unattached chip would expand by only 3 microns over the same temperature rise. However, the chip is commonly bonded to the module by solder balls, which are substantially inflexible. Consequently, thermal stresses tend to develop at the solder joints. The thermal stresses may reduce, the reliability of the solder connection. In particular, the lifetime of the solder connections may be substantially reduced as a consequence of variations in stress/strain caused by thermal cycling during normal chip operation.
A solder joint that is repetitively thermally cycled may eventually fail from the cumulative effects of multiple thermal cycles. Fatigue lifetime is commonly defined as the lifetime associated with the number of applied repeated stress cycles a material can endure before failure. Generally, the fatigue lifetime of solder joints decreases with increasing thermal stress on the solder joints during each thermal cycle. Thus, the fatigue lifetime will tend to decrease as the chip size is increased and/or the temperature swing increases, because these factors increase the thermal stresses. Fatigue lifetime tends to increase somewhat when comparatively soft solder joints are utilized. A comparatively soft solder, such as a 95% lead/5% tin solder, permits some limited flexure of the solder joint, which reduces thermal stresses at the solder joints compared with a hard, inflexible solder joint. However, even with comparatively soft solder connections, the solder joints are substantially inflexible. Large thermal stresses will tend to occur at solder joints near the edges of the chip. Consequently, the fatigue lifetime may not be as large as desired, particularly if the chip has a comparatively large area and is thermally cycled over a large temperature range.
One technique to improve the fatigue lifetime of the solder connections in a flip-chip bonding process is the use of a low stress epoxy underfill encapsulant. An epoxy underfill encapsulant substantially fills in the voids between the surfaces of the chip and module around the solder ball connections. An underfill encapsulant can redistribute stresses and strains over the entire chip area rather than having the stresses and strains concentrated near the comer solder joints of the chip. Additionally, the thermal coefficient of expansion (TCE) of the underfill encapsulant may be substantially matched to that of the solder, which reduces thermal stresses/strains at the solder joints. An underfill encapsulant also offers other potential advantages, such as protecting the chip from moisture, mechanical pull, mechanical shear, and shock/vibration.
There are two main processes which are commonly used to underfill a flip-chip bonded wafer.
FIG. 1
shows the steps of a liquid flow encapsulation process utilizing capillary action to flow a liquid encapsulant into the gaps between scolder joints of a chip mounted on a substrate. The package is then heat treated to cure the encapsulant. However, an underfilling process utilizing capillary action imposes limitations on the viscosity of the liquid encapsulant and the methods to flow/inject encapsulant into the voids. In particular, the processing conditions must be selected to minimize the possibility that deleterious voids are formed. An underfill process that results in voids in the encapsulation is undesirable because the voids may prevent the encapsulation from effectively redistributing thermal stresses. There are also significant manufacturing problems associated with a liquid underfilling process using capillary action. One disadvantage is that a process utilizing capillary action can require up to twenty to thirty minutes to ensure that the liquid encapsulant has sufficient time to properly flow, which is inconsistent with a high through-put process. Another disadvantage is that there are limitations on the types of materials that can be used as the encapsulant. For example, materials with a comparatively high viscosity or which significantly shrink during curing may be unsuitable encapsulants for a liquid flow encapsulation process because these liquid encapsulant properties increase the possibility of the formation of deleterious voids. For examples a viscous liquid encapsulant has a high resistance to fluid flow, which increases the possibility of creating a void whereas an encapsulant that significantly shrinks during curing may expand the size of voids, exacerbating the problem of void formation.
Another commonly used underfilling process is the so-called “no-flow” en
Peters Michael G.
Takahashi Yasuhito
Wang Wen-chou Vincent
Zhou Dashun S.
Coudert Brothers
Fujitsu Limited
Lee Granvill
Smith Matthew
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