Flip chip package structure

Details Flip chip package structure Flip chip package structure

2003-06-06

2004-06-08

Clark, S. V. (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

Insulating material

C257S707000

Reexamination Certificate

active

06747350

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, and more specifically to a flip chip package structure.
2. Description of the Related Art
Referring to
FIG. 7A
, a traditional flip chip package structure
700
is shown. The so-called flip chip technology is typically processed as follows. First, a plurality of conductive bumps
790
are formed on an active surface of IC chip
180
, or respectively on a plurality of contacts
710
on a surface of substrate
702
. Then, the active surface of IC chip
180
is turned downward in order to attach IC chip
180
to substrate
702
. Finally, an encapsulant
770
is formed between IC chip
180
and substrate, and further fills among the conductive bumps
790
.
Compared with the traditional wire bonding package structure, the layout of the bonding wires requires larger area. According to a typical flip chip package structure, the joints between IC chip and substrate are only distributed in the range of the surface area of the IC chip. The area of the flip chip package structure or substrate, supporting an I/O count less than 200, can be reduced to as little as 1.2 times that of the IC chip or less, the so-called chip scale package (CSP). However, I/O counts for some IC chips, such as CPU, graphics processing unit (GPU), chipset, or other types of system-on-chip (SOC) designs, are usually more than 300, or even more than 1000, resulting from their multiple functions and high working frequency, all of which require substrates used therein to bear complicated wiring. Therefore, it is difficult for the package structure with such high I/O counts and substrates used therein to be designed as CSP. Compared with the traditional wire bonding package structure, the flip chip package structure provides higher packaging density (greater I/O counts) and performance (shorter possible leads, lower inductance, and better noise control), smaller device footprints, and a lower packaging profile, the flip chip package structures, no matter CSP or non-CSP, are becoming more and more popular.
Due to the demand for small-aspect, light and powerful electronic products, it is necessary for a design rule of a substrate for a flip chip package structure to lay out denser wiring in a limited area of the substrate. It is difficult to add VSS or VDD to the transmission line in the wiring of the substrate to shield the transmission line, resulting in mutual inductance and mutual capacitor, which creates crosstalk in the neighboring trace lines when a signal transition arrives at a trace line, thereby negatively affecting signal quality, system stability, and specifically the character impedance of the transmission line.
One of the important factors affecting the design of a transmission line for a substrate for IC package or other kind of circuit board is impedance matching. A basic structure of the transmission line usually has a first trace line connecting a signal from an output end to a load end, and a second trace line connecting the load end to the output end, thus constructing a circuit. It output impedance of the signal is ZG, load impedance of the signal is ZL, and character impedance of the transmission line is Z
0
in the transmission line, the impedance match is denoted as ZG=Z
0
=ZL. According to the load end, the energy and signals in the transmission line will be completely transmitted to the load end when Z
0
=ZL. A part of the energy and signals will reflect back to the output end when impedance mismatch occurs from the variation in character impedance of the transmission line caused by the effects of crosstalk, resulting in overshoot, undershoot, ringback, and further negative affecting the integrity of the signal. Not only are signal quality and system stability negatively affected, but the electronic device may also be damaged. When the character impedance of the transmission line is controllable and adjustable, the design of a transmission line for a substrate for IC package or other kind of circuit board is therefore easier.
Furthermore, referring to the flip chip package structure
700
shown in
FIG. 7A
, IC chip
180
will be mechanically damaged in a subsequent process because IC chip
180
is a bare die.
A technology providing electromagnetic protection of a flip chip package structure from external radio frequency interference (RFI) and electromagnetic interference (EMI) is disclosed in U.S. Pat. No. 5,331,059, disclosing a flip chip package structure having an electrically conductive material covering an exposed semiconductor device and underfill material. The electrically conductive material electrically connects to a grounding pad on a substrate, providing electromagnetic protection for the flip chip package structure, specifically for the exposed semiconductor device. U.S. Pat. No. 5,371,404 discloses a flip chip package structure with a molding compound covering an IC chip and underfill of the flip chip package structure. The molding compound, typically filled approximately 70% to 75% with metallic composition to provide electrical and thermal conductivity, is formed overlying an underfill-formed substrate with a ground pad. The ground pad further connects to an exterior grounding device, thus grounding the flip chip package structure, specifically the IC chip, so as to provide electromagnetic protection for protecting the flip chip package structure from RFI and EMI. The molding compound further comprises a plurality of fins on a top surface further providing heat dissipation for the flip chip package structure.
FIGS. 1A through 1C
illustrate a heat spreader (sink) 32 disclosed in U.S. Pat. No. 5,977,626 and Japanese Patent Publication No. P2000-77575A.
FIG. 1A
illustrates a top view of heat spreader
32
,
FIG. 1B
illustrates a cross-section of heat spreader
32
, and
FIG. 1C
is a cross-section illustrating an application of heat spreader
32
in a flip chip package structure. In
FIG. 1A
, the heat spreader
32
has a plane
32
a
, a protruding portion
32
b
, a supporting member
32
c
on the central portion of the protruding portion
32
b
, and four supporting members
32
d
on the bottom of the plane
32
a
and at the corners of the plane
32
a
. In
FIG. 1B
, a cross-section of the heat spreader
32
along the line AA in
FIG. 1A
is shown. In
FIG. 1C
, a die
22
with a plurality of, solder bumps
26
a
is attached to a surface of substrate
20
using flip chip technology; an underfill
24
a
is filled under the die
22
and among the solder bumps
26
a
; the heat spreader
32
is attached to the substrate
20
by connecting the supporting member
32
c
to the die
22
and connecting the supporting members
32
d
to the surface of the substrate
20
using attaching material
34
to create electrical connection between the substrate
20
and heat spreader
32
; a molding compound
30
is formed covering the heat, spreader
32
but exposing the protruding portion
32
b
. The heat dissipation of the heat spreader
32
for die
22
is provided by the exposure of the protruding portion
32
b
and the connection between the die
22
and supporting portion
32
c
. The electromagnetic protection by the heat spreader
32
for die
22
is provided by the electrical connection between supporting portions
32
d
and substrate
20
, and the connection between the die
22
and supporting portion
32
c.
Referring to
FIG. 2
, a CSP structure disclosed by Taiwan, R.O.C Patent Publication No. 410445 and U.S. Pat. No. 6,255,140 is shown. The CSP structure has a heat slug
312
covering a die
311
attached to a substrate
313
using flip chip technology. The edges of the heat slug
312
connect to the extensive portion of an underfill layer
317
between the die
311
and substrate
313
using an adhesive epoxy
314
which provides thermal conductivity. The heat slug
314
may further electrically connect to substrate
313
to enhance its electromagnetic protection for die
311
.
The aforementioned arts provide electromagnetic protection for an IC chip

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