Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Flip chip
Reexamination Certificate
2000-03-29
2001-05-08
Flynn, Nathan (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Flip chip
C257S784000
Reexamination Certificate
active
06229219
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the packaging of integrated die circuits, and in particular, to the flip chip packaging of integrated circuits and a method of performing the same.
DESCRIPTION OF RELATED ART
Electronic components utilizing integrated circuit chips are used in a number of applications. Controlled Collapse Chip Connection is an interconnect technology developed as an alternative to wire bonding. This technology is generally known as C4 technology, or flip chip packaging. Broadly stated, one or more integrated circuit chips are mounted above a single or multiple layer substrate and pads on the chip are electrically connected to corresponding pads on a substrate by a plurality of electrical connections, such as solder bumps. The integrated circuit chips may be assembled in an array such as a 10×10 array. A substrate is then electrically connected to another electronic device such as a circuit board with the total package being used in an electronic device such as a computer.
In general, flip chip joining is desirable for many applications because the footprint or area required to bond the chip to the substrate is approximately equal to the area of the chip itself. Flip chip joining also exploits the use of a relatively small solder bump which typically measures a height of approximately 1 mil to 1.5 mil and a width of approximately of 2 to 4 mils to join the pad on a chip to a corresponding pad on the substrate. Electrical and mechanical interconnects are formed simultaneously by reflowing the bumps at an elevated temperature. The C4 joining process is self-aligning and the wetting action of the solder will align the chip's bump pattern to the corresponding substrate pads. This action compensates for chip to substrate misalignment, up to several mils, incurred during chip placement.
Different integrated circuit dies have different die footprints. A die footprint is characterized by the pattern of conductive pads on the surface of the die. In conventional packages, a footprint is provided that exactly matches (a mirror reflection) the die footprint of a particular integrated circuit die. Hence, when a die is flipped onto the package, the conductive pads of the die correspond on a one-to-one basis with the conductive pads of the package. This is due to the package footprint being an exact mirror duplicate of the die footprint.
As stated earlier, however, different dies will have different footprints. In certain technologies, an enhanced version of an integrated circuit die may have a different die footprint. However, it is normally desirable to use the same package since the external connections of the package may be the same for standardizing the connections of an assembled integrated circuit die package to a circuit board. In order to properly connect to a second die, a conventional package needs a different package footprint than the package footprint used with a first die. In other words, the same package cannot normally be used to connect to different integrated circuit dies having different die footprints. This increases the overall cost of manufacture since multiple types of packages are needed for multiple types of integrated circuit dies. Also, the same package cannot be re-used to receive a different integrated circuit die, having a different die footprint. Such a feature is desirable to allow upgrading of an integrated circuit without disturbing the connection of the package to the circuit board.
SUMMARY OF THE INVENTION
There is a need for a flip chip package that is compatible with multiple die footprints, and a method of assembling a package that accommodates different dies, having different footprints.
These and other needs are met by embodiments of the present invention which provide a flip chip package compatible with first and second die footprints. The flip chip package of the invention comprises an interconnection substrate having a connection surface configured to receive an integrated circuit die that has either a first or second die footprint. Each die footprint comprises a plurality of conductive pads on the surface of the integrated circuit die. A plurality of conductive pads of the first die footprint have a different pattern than the plurality of conductive pads of the second die footprint. The interconnection substrate has a plurality of conductive pads on its connection surface. These conductive pads establish a connection to the conductive pads of an integrated circuit die. The connection surface conductive pads have a first section corresponding to the conductive pads of an integrated circuit with a first die footprint. The connections surface conductive pads also have a second section corresponding to the conductive pads of an integrated circuit with a second die footprint. The first and second sections of the connection surface conductive pads overlap so that at least one of the connection surface conductive pads in the first section is also one of the connection surface conductive pads in the second section.
The provision of a package with conductive pads arranged with overlapping first and second sections configured to correspond to the different footprints of first and second dies allows the same package to be used with different dies. At the same time, the package size does not need to be increased beyond the size of the larger die footprint since the two sections of conductive pads overlap one another.
The earlier stated needs are also met by another embodiment of the present invention which provides a method of assembling a flip chip package with either a first integrated circuit die having a plurality of conductive pads arranged in a first die footprint or a second integrated circuit die having a plurality of conductive pads arranged in a second die footprint different from the first die footprint. The method comprises the steps of selecting an integrated circuit die for flip chip connection to an interconnection substrate with a connection surface having a plurality of conductive pads. The integrated circuit die has either the first die footprint or the second die footprint. The selected integrated circuit die is positioned with respect to the interconnection substrate so that all of the conductive pads of the selected integrated circuit die contact a respective one of the connection surface conductive pads upon flipping the integrated circuit die onto the interconnection substrate. The integrated circuit die is then flipped onto the interconnection substrate.
One of the advantages of the present invention is that it allows different integrated circuit dies to be selected for flip chip connection to the interconnection substrate of the flip chip package. The selection of the integrated circuit die may be made regardless of whether it has a first die footprint or a second die footprint.
The foregoing and other features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.
REFERENCES:
patent: 5399898 (1995-03-01), Rostoker
patent: 5719440 (1998-02-01), Moden
patent: 5793101 (1998-08-01), Kuhn
patent: 5815372 (1998-09-01), Gallas
patent: 5930597 (1999-07-01), Call et al.
patent: 5952726 (1999-09-01), Liang
patent: 6002178 (1999-12-01), Lin
Bhagath Shrikar
Tain Alexander C.
Advanced Micro Devices , Inc.
Flynn Nathan
Forde Remmon R.
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