Flip chip package

Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Flip chip

Reexamination Certificate

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Details

C257S666000, C257S737000, C257S738000, C257S786000

Reexamination Certificate

active

06815833

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of Invention
This invention relates to a flip chip package. More particularly, the present invention is related to a flip chip package with a leadless lead frame.
2. Related Art
Integrated circuit (chip) packaging technology is becoming a limiting factor for the development in packaged integrated circuits of higher performance. Semiconductor package designers are struggling to keep pace with the increase in pin count, size limitations, low profile, and other evolving requirements for packaging and mounting integrated circuits. Nowadays, ball grid array package (BGA) and chip scale package (CSP) are wildly applied to chip package with high I/Os and assembly package for thermal enhance integrated circuits.
However, assembly package with lead frame possesses great marketing for that it can provide low-cost solutions for current semiconductor package. Due to lead frame with long inner leads and outer leads, such conventional lead frame assembly package can not applied to chip scale package and low profile package. Thus leadless assembly package is wildly provided in the semiconductor package industry to reduce the size of the assembly package in the recent years. Referring to
FIGS. 1 and 2
, a conventional leadless assembly package is disclosed. The leadless assembly package
100
mainly comprises a leadless lead-frame
110
, a chip
120
, an encapsulation
130
and a plurality of conductive wires
140
. The lead frame
110
has a plurality of leads
110
a
, a die paddle
110
b
and four tie bars
110
c
. Each tie bar
110
c
is connected to the die paddle
110
b
as shown in FIG.
2
. In addition, the die
120
is disposed on the die paddle
110
b
of the leadless lead frame
110
by an adhesive layer
150
, and is electrically connected to the leads
110
a
of the leadless lead frame
110
through the conductive wires
140
. And the encapsulation
130
encapsulates the leadless lead frame
110
, the die
120
and the conductive wires
140
.
The die paddle
110
b
of the leadless assembly package
100
exposes to the bottom of the leadless assembly package
100
so as to improve the thermal performance of the leadless assembly package. Moreover, due to the short leads, the impedance will be lower. Accordingly, the leadless assembly package is especially adapted to the assembly package with high-frequency devices, which are performed at the frequency from 10 GHz to 100 GHz, enclosed therein. In such a manner, such leadless assembly package has low cost and competitive price. Therefore the leadless assembly package is adapted to cell phone, personal digital application (PDA), digital camera and information application (IA).
The wire-bonding method is utilized to manufacture conventional leadless assembly packages, so the signal is transmitted through the wires. Therefore the impedance will become higher when the high frequency signal is transmitted in the assembly package. Accordingly, a flip chip package is disclosed to reduce the impedance by using bumps for transmitting signal. However, when the bumps are attached to the die paddle of the lead frame, the die is dislocated so as to cause the bumps not to connect the leads well. Moreover, the die is tilted to cause the die to be damaged.
Consequently, providing another leadless package to solve the mentioned-above disadvantages and disposing the die on the lead frame precisely is the most important task in this invention.
SUMMARY OF THE INVENTION
In view of the above-mentioned problems, an objective of this invention is to provide a flip chip package adapted to a leadless assembly package, which can make the die disposed on the lead frame precisely.
To achieve the above-mentioned objective, a flip chip package adapted to leadless assembly package is provided, wherein the flip chip package at least comprises a chip and a lead frame. The lead frame has a die paddle and a plurality of leads, and the chip has a plurality of bonding pads formed on the active surface of the chip. In addition, a plurality of bumps formed on the bonding pads not only electrically connect the chip and the die paddle but also electrically connect the chip and the leads. Therein the bumps electrically connected to the die paddle not only prevents the die from being dislocated but also is regarded as paths for grounding and transmitting heat.
Besides, at least one of the plural leads has a first concavity and the die paddle has at least one second concavity corresponding to one of the bonding pads. Accordingly, when the chip is flipped and mounted to the lead frame, the bumps can be disposed in the first concavities and the second concavities securely. Consequently, the die can be attached to the lead frame securely and prevent the die from being dislocated. Moreover, the die will not be tilted and cause the die to be connected to the lead frame well. In addition, a plurality of another concavities can be formed at the tie bars to further fix the die to the lead frame.
Accordingly, the bumps connecting the chip and the die paddle or connecting the chip and the tie bars can be another heat dissipation paths and grounding paths.


REFERENCES:
patent: 5091341 (1992-02-01), Asada et al.
patent: 5217922 (1993-06-01), Akasaki et al.
patent: 5378924 (1995-01-01), Liang
patent: 5753969 (1998-05-01), Suzuya et al.
patent: 6282094 (2001-08-01), Lo et al.
patent: 6314639 (2001-11-01), Corisis
patent: 6331451 (2001-12-01), Fusaro et al.
patent: 6355502 (2002-03-01), Kang et al.
patent: 6583513 (2003-06-01), Utagikar et al.

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