Flip chip interface circuit of a semiconductor memory device

Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Flip chip

Reexamination Certificate

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Details

C257S666000, C257S678000, C257S723000, C438S106000, C438S108000, C438S123000

Reexamination Certificate

active

07005748

ABSTRACT:
A flip chip interface circuit for combining two identical semiconductor chips on upper and lower surfaces of an assembling lead frame into one flip chip package includes at least first and second address pads and first and second bonding option pads formed symmetrically on the chips in a mirror type arrangement to each other. The first and second address pads are input with a signal for selecting operations of the first and second semiconductor chips. The first and second input pad selection and chip selection signals are output in response to signals from the first and second address pads and first and second bonding option pads of the chips, the first and second semiconductor chip selection signals are output in response to the first and second input pad and chip selection signals, and an interface enable signal is output in response to the first and second semiconductor chip selection signals.

REFERENCES:
patent: 5633833 (1997-05-01), Yoon
patent: 5701031 (1997-12-01), Oguchi et al.
patent: 5744827 (1998-04-01), Jeong et al.
patent: 5757080 (1998-05-01), Sota
patent: 5880531 (1999-03-01), Hagiya et al.
patent: 6317377 (2001-11-01), Kobayashi
patent: 6430717 (2002-08-01), Noji
patent: 6566760 (2003-05-01), Kawamura et al.
patent: 6593646 (2003-07-01), Callahan
patent: 2002/0000672 (2002-01-01), Mori
patent: 2003/0075789 (2003-04-01), Kawamura et al.

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