Flip-chip integrated circuit with improved testability

Details Flip-chip integrated circuit with improved testability Flip-chip integrated circuit with improved testability

1996-09-30

1998-02-17

Saadat, Mahshid D.

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Configuration or pattern of bonds

257776, H01L 2348, H01L 2352, H01L 2940

Patent

active

057194491

ABSTRACT:
An integrated circuit is adapted for implementing flip-chip technology with solder bumps, while providing for improved testability. The integrated circuit comprises two sets of pads formed in the same metal layer, with a first set being used for wafer probing, and a second set for solder bumps. The wafer probe pads are placed in one row along each chip edge. A second set of pads, the solder bump pads, are arranged in rows towards the center of the chip with respect to the wafer probe pads. Metal interconnects formed in the same metal layer as the pads connects each solder bump pad to a corresponding wafer probe pad. Testing of the integrated circuit may be accomplished using the wafer probe pads according to conventional techniques, while mounting of the chip may be accomplished with the solder bump pads using the flip-chip technology.

REFERENCES:
patent: 4488267 (1984-12-01), Harrison
patent: 5206585 (1993-04-01), Chang et al.
patent: 5212406 (1993-05-01), Reele et al.
patent: 5334857 (1994-08-01), Mennitt et al.
patent: 5594273 (1997-01-01), Dasse et al.
T.D. Dudderar et al.,"AT&T.mu.Surface Mount Assembly: A New Technology for the Large Volume Fabrication of Cost Effective Flip-Chip MCMs", Proceedings of the 1994 International Conference on Multichip Modules, sponsored by IEEE,Apr. 13-15, 1994, Denver, Colorado, pp. 266-272.
Joel Darnauer et al., "Fast Pad Redistribution from Periphery-IO to Area-IO", 1994 IEEE Multi-Chip Module Conference MCMC-94, Mar. 15-17, 1994, Santa Cruz, California, pp. 38-43.
Ray-Long Day et al.i, "A Silicon-on-Silicon Multichip Module Technology with Integrated Bipolar Components in the Substrate", 1994 IEEE Multi-Chip Module Conference MCMC-94,Mar. 15-17, 1994, Santa Cruz, California, pp. 64-67.

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