Flip-chip integrated circuit routing to I/O devices

Details Flip-chip integrated circuit routing to I/O devices Flip-chip integrated circuit routing to I/O devices

1998-06-03

2001-05-01

Picardat, Kevin M. (Department: 2823)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

C438S107000, C438S108000, C438S613000

Reexamination Certificate

active

06225143

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention concerns routing of electrical connections during the design of flip-chip integrated circuits (ICs), and particularly relates to routing of electrical connections from bump pads to input/output devices on an IC.
2. Description of the Related Art
Certain IC chips (or dies), called wire-bond ICs, are fabricated with metal bonding pads along their periphery. These peripheral pads serve as terminals for connecting the die to external signals, including control signals, power and ground. Typically, the wire-bond IC die is mounted within a plastic or ceramic package having multiple pins, and wire connections are made between the die's bonding pads and the package's pins. Finally, the package containing the IC die is mounted onto a printed circuit board in a manner so as to establish electrical connections between the pins of the IC and other components on the printed circuit board. In this manner, external signals can be provided to and from the IC die.
However, the foregoing fabrication method has its limitations. First, because only the periphery of the chip is used for external connection pads, the number of such pads for a given sized chip is limited. In particular, advances in technology which permit more and more gates to be placed within a given chip area have resulted in an increased demand for such pads, particularly power and ground pads. In certain cases, the design requires more pads than can be provided solely at the chip's periphery. Second, when all the pads are provided only at the chip's periphery, additional routing is required to bring the corresponding signals, particularly power and ground signals, to the interior logic of the chip. Third, in wire-bond chips the wire connections between the die and the package pins introduce additional resistance and inductance which sometimes can impair the chip's performance.
To overcome these problems, flip-chip techniques recently have been used. One example of a flip-chip configuration is shown in
FIG. 1
, which provides a cross-sectional view of a flip-chip
100
. Referring to
FIG. 1
, flip-chip
100
includes a semiconductor layer
102
, on which are formed transistors, resistors and other electronic devices, as well as some of the electrical connections between such electronic devices. Flip-chip
100
also includes one or more metal layers, such as metal layers
104
A and
104
B, which are used for providing the bulk of the electrical connections between the electronic devices formed on semiconductor substrate
102
. These metal layers generally are used primarily for the longer electrical connections, such as the connections between distant cells. By providing such metal layers, valuable space on the semiconductor layer
102
can be conserved for forming the electronic devices. Flip-chip
100
also includes a top layer
106
, on which are formed multiple solder bump terminals, such as solder bump terminal
108
, called bump pads. These bump pads are used as the input/output terminals for die
100
. As used herein, input/output and I/O refer to input-only, output-only or combined input and input.
Referring to
FIG. 1
, bump pad
108
contacts redistribution metal layer
107
. Redistribution metal layer
107
, in turn, connects to metal layer
104
B and metal layer
104
B connects to metal layer
104
A using vias
110
. Finally, semiconductor layer
102
connects to metal layer
104
A using contacts such as contact
111
, thereby completing the electrical connections between bump pads
108
and semiconductor layer
102
. Between layers
104
B and
107
and between metal layer
104
A and the semiconductor substrate
102
are electrically insulating layers
105
.
For mounting purposes, flip-chip die
100
typically is “flipped” so that top layer
106
faces downward. Top layer
106
then is bonded to a substrate. The substrate may be a passive carrier such as a printed circuit board, or it may be another semiconductor chip. Specifically, each bump pad
108
typically is solder bonded to a corresponding pad on the substrate, thereby forming the required electrical connections. The substrate then is usually bonded directly to a printed circuit board, on which additional flip-chips and/or ICs utilizing other types of packaging are mounted.
FIG. 2
provides a representational illustration of semiconductor substrate
102
. The logic circuitry of integrated circuit
100
is formed in the interior portion
120
of the semiconductor substrate
102
, while the periphery of semiconductor substrate
102
is used for the I/O devices. The logic portion
120
includes a number of functional circuit blocks that can have different sizes and shapes. The larger blocks can include, for example, central processing units such as CPU
121
, read-only memories such as ROM
122
, clock/timing units such as clock/timing unit
123
, random access memories such as RAMs
124
, and I/O units such as I/O unit
125
for providing an interface between CPU
121
and various peripheral devices. These blocks, commonly known as macroblocks, can be considered as modules for use in various circuit designs, and are represented as standard designs in circuit libraries. The logic portion also includes tens of thousands, hundreds of thousands or even millions or additional small cells
126
. Each cell
126
represents either a single logic element, such as a gate, or several logic elements interconnected in a standardized manner to perform a specific function. Cells that consist of two or more interconnected gates or logic elements are also available as standard modules in circuit libraries.
Along the periphery of semiconductor substrate
102
are various I/O devices or cells
116
. Each such I/O device has connected to it at least one pad
118
which provides a means for electrically connecting to the respective I/O device
116
. Pads
118
are, however, different from the bonding pads used in wire-bond IC devices. Rather than being used for wire bonding, pads
118
instead connect to metal traces on redistribution metal layer
107
by using a via. Accordingly, pads
118
generally can be significantly smaller than the wire bonding pads used in wire-bond integrated circuits.
I/O devices
116
receive power and ground by connecting to power (VDD) ring
132
and ground (VSS) ring
133
. Similarly, internal logic circuitry
120
receives external power and ground by connecting to power (VDD
2
) ring
130
and ground (VSS
2
) ring
131
. Typically, VDD
2
/VSS
2
for the internal logic circuitry
120
is provided on a circuit which is separate from the VDD/VSS rings for I/O cells
116
in order to prevent the higher power, and thus noisier, I/O cells from corrupting the logic processing.
To further isolate the power/ground supplies for certain sensitive circuits from the power/ground supplies for noisier circuits, often times cuts are made in the rings (not shown). Each resulting ring segment is then supplied by separate external power/ground signals and can be used to supply a different type of circuit. In addition, although only a single I/O power ring
132
is shown in
FIG. 2
, mixed-voltage integrated circuits may utilize a different power ring for each different voltage. Moreover, rather than providing power/ground rings
130
to
133
on substrate
102
, these power/ground rings often are implemented on a metal layer which is used as a dedicated power plane.
FIG. 3
is a representational view of the bump pad layout and trace connections of flip-chip die
100
. As noted above, top layer
106
includes bump pads, such as bump pads
140
to
144
. The redistribution layer
107
includes metal traces, such as traces
148
, which electrically connect the bump pads to other areas on the die
100
. For instance, each of bump pads
140
and
141
is connected using a trace
148
to VDD
2
ring
130
and VSS
2
ring
131
, respectively, which supply the internal logic circuitry
120
. Similarly, each of bump pads
142
and
143
is connected using a trace
148
to VDD

Affiliated with

Also associated with

Rating

Flip-chip integrated circuit routing to I/O devices does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Flip-chip integrated circuit routing to I/O devices, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Flip-chip integrated circuit routing to I/O devices will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2434798