Flip-chip having an on-chip cache memory

Details Flip-chip having an on-chip cache memory Flip-chip having an on-chip cache memory

1999-01-08

2001-01-16

Saadat, Mahshid (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Flip chip

C257S777000, C257S778000, C257S779000, C257S780000, C257S781000

Reexamination Certificate

active

06175160

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to a semiconductor chip and, more specifically, to a flip-chip having a cache memory device attached to the backside thereof.
2. Discussion of Related Art
Within the integrated circuit industry there is a continuing effort to increase integrated circuit speed as well as device density. As a result of these efforts, there is a trend towards using flip-chip technology when packaging complex high speed integrated circuits. Flip-chip technology is also known as control collapse chip connection (C4) technology. In flip-chip technology, the integrated circuit die is flipped upside down. By flipping the integrated circuit die upside down, ball bonds may be used to provide direct electrical connections from the bond pads of the die directly to a corresponding set of pads on a package.
In the following discussion reference will be made to a number of drawings. The drawings are provided for descriptive purposes only and are not drawn to scale.
In computer systems, the access of main memory to retrieve information often takes a substantial portion of the operational time. This occurs for various reasons. First, main memory is made of random access memory. Such memory is often sufficiently large such that the cost is kept within bounds by using relatively slow memory. Second, main memory is typically accessed over a system bus, which provides a less than optimum interface between the main memory and the central processing unit of the system.
For this reason, the use of cache memories to increase system speed has become prevalent. A cache memory makes use of a relatively small amount of fast random access memory in which recently used instructions and data are stored as they are used by the processor. Such instructions and data are then available in the cache to be more rapidly accessed by the associated processor when next required. The basic theory of caching is that, in general, information which has been recently used is more likely to be used sooner than is other information. The cache memory is often both physically faster than the random access memory used for main memory and arranged so that it may be addressed more rapidly than main memory.
Currently, cache memory for C4 packaged processor chips (flip-chips) is typically located off the chip onto a processor card or motherboard. Locating the cache memory off-chip produces delays caused by interfacing off-chip transfers. Cache memory may also be located on the processed die. The size of this type cache memory, however, is constrained by the combination of both economic and processing factors which limit how large an on-die cache can be. Thus, although the goal is always to put as much cache memory on the die as possible, it is still desirable to have as small a die as possible.
SUMMARY OF THE INVENTION
An integrated circuit device is disclosed. The integrated circuit device includes a semiconductor substrate having first and second opposing surfaces with circuit elements formed within the first surface. A plurality of raised bump contacts are located on the first surface and connected to the circuit elements. Additionally, a plurality of electrical interconnects are located on the second surface and connected to the circuit elements. A cache memory device is electrically coupled to the plurality of electrical interconnects located on the second surface.


REFERENCES:
patent: 5814891 (1998-09-01), Hirano
patent: 5883430 (1999-03-01), Johnson
patent: 5952726 (1999-09-01), Liang
patent: 5952727 (1999-09-01), Takano et al.
patent: 5956605 (1999-09-01), Akram et al.
patent: 5973403 (1999-10-01), Wark
patent: 5990545 (1999-11-01), Schueller et al.
patent: 6013944 (2000-01-01), Moriya et al.
patent: 6018196 (2000-01-01), Noddin
patent: 6025650 (2000-02-01), Tsuji et al.
patent: 6031284 (2000-02-01), Song
patent: 6043429 (2000-03-01), Blish, II et al.
patent: 403255657 (1991-11-01), None
patent: 406061368 (1991-11-01), None
patent: 404085961 (1992-03-01), None
patent: 406061383 (1994-03-01), None
patent: 7-184178 (1995-07-01), None

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