Flip chip design on a coplanar waveguide with a...

Details Flip chip design on a coplanar waveguide with a... Flip chip design on a coplanar waveguide with a...

2001-07-20

2003-09-23

Flynn, Nathan J. (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Flip chip

C257S786000, C257S737000, C257S695000, C257S691000, C257S664000

Reexamination Certificate

active

06624521

ABSTRACT:

TECHNICAL FIELD
The present invention is generally related to integrated circuits and, more particularly, is related to a flip chip assembly and method for producing a flip chip assembly.
BACKGROUND OF THE INVENTION
Along with rapid advances in microwave and millimeter wave system development throughout the last few years, the choice of the packaging interconnection solution has become a very important issue. For microwave circuit applications, as well as other applications, low cost, high density and short transition interconnect are considered to be the main advantages of the flip chip technique.
A flip chip is a semiconductor chip or die that has bumped terminations spaced around the active surface of the die and is intended for face-two-face attachment to a substrate or another semiconductor die. The bumped terminations of the flip chips are usually in the configuration of an array of balls. In this configuration, an array of minute balls or bumps are disposed on an attachment surface of a semiconductor die. The attachment of a flip chip to a substrate or another semiconductor involves aligning the balls or bumps on the flip chip with a plurality of contact points (configured to be a mere image of the bump arrangement on the flip chip) on a facing surface of the substrate. A plurality of bumps may also be formed on a facing surface of the substrate at the contact point. A quantity of liquid flux is often applied to the face of the chip and/or substrate, and the chip and substrate are subjected to an elevated temperature to affect refluxing or soldering of the bumps on the chips and/or corresponding bumps on the substrate.
FIG. 1
is a side view of a conventional flip chip assembly
100
. The flip chip
100
of
FIG. 1
shows a coplanar waveguide
110
to coplanar waveguide
110
transition. The coplanar waveguides are attached to a mounting substrate
130
. The attached chip is connected to the mounted substrate
120
. The coplanar waveguides
110
are connected to the attached chip via ground bumps
140
.
FIGS. 2A and 2B
represent top views of the conventional coplanar waveguide
110
of the flip chip assembly
100
of FIG.
1
. The coplanar waveguide
110
includes a transmission line
150
and a signal bump
160
placed thereon. Around the transmission line
150
, the mounting substrate
130
is exposed. On the coplanar waveguide
110
are attached a single ground bump
140
on either side of the signal bump
160
.
FIG. 2A
shows the configuration of the single bump
140
on each side of the signal bump
160
, and
FIG. 2B
depicts two ground bumps
140
on each side of the signal bump
160
.
FIG. 2C
is a top view of an attached chip
170
that is placed on the coplanar waveguide
110
of
FIGS. 1A and 2B
to form the conventional flip chip assembly
100
depicted in FIG.
1
.
There are numerous variations to the standard flip chip attachment technique. For example, U.S. Pat. No. 5,329,423 issued Jul. 12, 1994 to Scholz relates to a demountable flip chip assembly comprising a first substrate having a contact site with raised bump and a second substrate having a depression for a contact site. The raised bumps are pressed into the depressed areas to electrically and mechanically connect the first substrate to the second substrate without using reflowed solder. Thus, the first substrate can be removed from the second substrate without damaging either substrate.
U.S. Pat. No. 5,477,086 issued Dec. 19, 1995 to Rostoker et al. relates to a flip chip attachment technique involving forming a concave conductive bump on one substrate (such as the printed circuit board) to receive and align the solder balls on the other substrate (such as the semiconductor die). The solder balls and/or the concave conductive bump are reflowed to fuse them together.
It is also known in the art that conductive polymers or resins can be utilized in place of solder balls. U.S. Pat. No. 5,258,577 issued Nov. 2, 1993 to Clements relates to a substrate and a semiconductor die with a discontinuous passivation layer. The discontinuities result in vias aligned with the contact points between the substrate and the semiconductor die. A resin with spaced conductive metal particles suspended therein is disposed within the vias to achieve electrical contact between the substrate and the semiconductor die. U.S. Pat. No. 5,468,681 issued Nov. 21, 1995 to Pasch relates to interconnecting conductive substrates using an interposer having conductive plastic-filled vias.
Such flip chip and substrate attachments (collectively “electronic packages”) are generally comprised of dissimilar materials that expand at different rates on heating. The most severe stress is due to the inherently large thermal coefficient of expansion (“TCE”) mismatch between the plastic and the metal. These electronic packages are subject to two types of heat exposures: process cycles which are often high in temperature but few in number; and operation cycles, which are numerous but less extreme. If either the flip chip(s) and/or substrate(s) are unable to repeatedly bear their share of the system thermal mismatch over its lifetime, the electronic package will fracture, thereby destroying the functionality of the electronic package.
As an electronic package dissipates heat to its surroundings during operation, or as the ambient system temperature changes, differential thermal expansions cause stresses to be generated in the interconnection structure (solder ball bonds) between the semiconductor die and the substrate. These stresses produce instantaneous elastic and, most often, plastic strain, as well as time-dependent (plastic and elastic) strains in the interconnection structure, particularly at the weakest interconnection structure. Thus, the thermal expansion mismatch between chip and substrate will cause a shear displacement to be applied on each terminal which can fracture the solder connection.
The problems associated with thermal expansion match are also applicable to connections made with conductive polymers or resins. After curing, the polymers or resins become substantially rigid. The rigid connections are equally susceptible to breakage due to thermal expansion mismatch.
Thus, a heretofore unaddressed need exists in the industry to address the aforementioned deficiencies and inadequacies.
SUMMARY OF THE INVENTION
The present invention provides a flip chip assembly and method for producing a flip chip assembly.
Briefly described, one embodiment of the system, among others, can be implemented as follows. A flip chip assembly includes a coplanar waveguide transmission line launch and a bump interconnection that includes multiple ground bumps wherein the ground bumps are arranged in a pseudo-coaxial configuration. Further, the transmission line maybe a radial transmission line which facilitates the pseudo-coaxial vertical transition. The number of bumps may be, for example but not limited to, two, four, six, or eight or more than eight. Further, the bumps may not necessarily be arranged in a pseudo-coaxial configuration if a radial transmission line is used.
The present invention can also be viewed as providing methods for producing a flip chip assembly. In this regard, one embodiment of such a method, among others, can be broadly summarized by the following steps: providing a coplanar waveguide transmission line launch; arranging at least one ground bump on a pseudo-coaxial configuration; and forming a bump interconnection. The transmission line may be a radial transmission line. The multiple ground bumps may range in number, for example but not limited to, two, four, six, eight or more. Additionally, if a radial transmission line is used, the multiple ground bumps maybe arranged in a non-pseudo-coaxial configuration.
Other assemblies, methods, features, and advantages of the present invention will be or become apparent to one with skill in the art upon examination of the following drawings and detailed description. It is intended that all such additional methods, features, and advantages be included within this description, be withi

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