Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Configuration or pattern of bonds
Reexamination Certificate
2000-06-15
2004-01-27
Nadav, Ori (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Configuration or pattern of bonds
C257S778000, C257S779000, C257S784000
Reexamination Certificate
active
06683387
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a member for seating a semiconductor device, and more particularly to a ceramic or an organic carrier member having adapted landing pads thereon for mounting a bumped semiconductor device.
2. Background Art
In a conventional flip chip assembly or package, an integrated circuit (IC) die or chip, as well as other semiconductor devices, are “bumped” with solder, i.e. a plurality of discrete solder bumps are formed over metal contacts on the surface of the die. The chip is then turned upside down or “flipped” so that the device side or face of the IC die can be coupled to the carrier member, such as a ceramic or plastic carrier member having balls, pins or land grid arrays. The solder bumps of the device are attached to the carrier member to form an electrical and mechanical interconnection between the device and the carrier member. Directly coupling an IC die or chip to the carrier member by the use of an array of solder bumps accommodates an increased number of input/output (I/O) terminals and provides electrical signals immediately below the chip, improving voltage noise margins and signal speed.
As illustrated in
FIG. 1
, a conventional flip chip assembly
8
includes a device or IC die
10
mechanically and electrically attached to substrate
16
by a plurality of solder bumps
12
connected to solder pads
14
on substrate
16
. Solder pads
14
are electrically connected to pin leads
18
by internal wiring (not shown for illustrative convenience) throughout substrate
16
. Pin leads
18
are used to provide electrical connections to external circuitry. The assembly, thus, provides an electrical signal path from IC die
10
through solder/pad connections
12
/
14
through substrate
16
, by way of internal wiring, to an external circuitry by way of pin leads
18
.
As shown, substrate
16
has a plurality of solder pads
14
, which are generally formed by screen printing a coating of solder on the substrate. Solder bumps
12
on die
10
are generally formed by known solder bumping techniques and are conventionally formed of a high lead (Pb) solder, such as solders having from 97-95 wt % Pb and from 3-5 wt % of tin (Sn). Substrate
16
can be made of ceramic or plastic materials. When the substrate is made of a ceramic, the electrical and mechanical interconnect between the die and substrate is conventionally achieved by reflowing the solder pads
14
and solder bumps
12
at a relatively high temperature, such as 350° C. to 370° C., to join solder bumps
12
and pads
14
between the die and substrate
16
. It is preferable to have the high melting interconnection on the die to avoid degradation of the die/substrate interconnection in subsequent thermal processing steps.
Attaching a bumped die to a substrate involves aligning the bumped die to an array of solder pads on the substrate and then contacting the bumps on the device to the solder pads on the substrate. Once the device is in contact with the solder pads, the solder is reflowed to form an electro-mechanical interconnection thereby securing the device to the substrate. Reflowing the solders is typically carried out by moving the aligned assembly into a heated furnace.
One problem associated with this process, however, is proper alignment of the device to the array of solder pads on the substrate. Further, once the aligned device is placed on the substrate, there is a tendency for the die to move off of the solder pads, particularly when the assembly is placed into a furnace or during reflow of the solder pads to the form the electro-mechanical interconnection in the furnace. As the density of interconnects increases and the need for lighter and smaller packages increase, the problems associated with attaching IC dies and capacitors to substrates are exacerbated.
Accordingly, a continuing need exists in the art for improved methods of attaching dies with a higher density of interconnects while forming reliable electro-mechanical interconnections between the die and the carrier member.
SUMMARY OF THE INVENTION
An advantage of the present invention is a carrier member suitable for seating a device thereto.
Additional advantages and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the invention. The advantages of the invention may be realized and obtained as particularly pointed out in the appended claims.
According to the present invention, the foregoing and other advantages are achieved in part by a carrier member for seating a device having a plurality of solder terminals, such as a bumped IC die, capacitor, etc. The carrier member comprises: a substrate having a plurality of landing pads thereon and a plurality of leads on the substrate that are in electrical communication with the landing pads. In accordance with the present invention, at least one of the plurality of landing pads is adapted to receive the device to be mounted thereto. Advantageously, at least one of the landing pads has a depression or cavity therein such that at least one of the solder terminals on the device rests in the depression thereby seating the device and preventing the device from moving off of the plurality of landing pads on the substrate.
Embodiments of the present invention include a substrate having a plurality of landing pads arranged in a grid array wherein at least two landing pads of the periphery of the grid array have depressions or cavities therein and wherein the landing pads comprise eutectic solder, i.e., solder containing about 63 wt % tin and about 37 wt % lead. In an embodiment of the present invention, the substrate is a ceramic material or an organic substrate comprising an organic resin, with optionally fiberous materials, such as glass fibers, throughout the resin. The organic substrate can be a laminated structure with alternating insulative and conductive layers. Alternatively, the organic substrate can be fabricated as a non-laminated structure, such as a molded plastic part with internal wiring.
Another aspect of the present invention is a method of manufacturing a carrier member having at least one adapted landing pad. The method comprises providing a carrier member for seating a device, wherein the carrier member comprises a substrate having a plurality of landing pads thereon and a plurality of leads on the substrate which are in electrical communication with the landing pads; and forming a depression or cavity in at least one of the plurality of landing pads so that a terminal of a device can be received in the depression when the device is mounted on the carrier member to seat the device.
Embodiments of the present invention include forming the plurality of landing pads with eutectic solder and forming the depression by coining or stamping at least one landing pad to form the depression or cavity.
Additional advantages of the present invention will become readily apparent to those skilled in this art from the following detailed description, wherein only the preferred embodiment of the present invention is shown and described, simply by way of illustration of the best mode contemplated for carrying out the present invention. As will be realized, the invention is capable of other and different embodiments and its several details are capable of modifications in various obvious respects, all without departing from the present invention. Accordingly, the drawing and description are to be regarded as illustrative in nature, and not as restrictive.
REFERENCES:
patent: 5853517 (1998-12-01), Petefish et al.
patent: 5940679 (1999-08-01), Tomura et al.
patent: 6228676 (2001-05-01), Glenn et al.
patent: 6291775 (2001-09-01), Saitoh
patent: 7-231050 (1995-08-01), None
Advanced Micro Devices , Inc.
Nadav Ori
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