Metal fusion bonding – Process – Plural joints
Reexamination Certificate
2003-09-03
2004-10-05
Silverman, Stanley S. (Department: 1754)
Metal fusion bonding
Process
Plural joints
C228S165000, C438S029000, C438S694000
Reexamination Certificate
active
06799713
ABSTRACT:
CLAIM OF PRIORITY
This application makes reference to and claims all benefits accruing under 35 U.S.C. Section 119 from an application entitled, “FLIP-CHIP BONDING STRUCTURE AND METHOD FOR MAKING THE SAME,” filed in the Korean Industrial Property Office on Mar. 5, 2002 and there duly assigned Serial No. 2002-11511.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a flip-chip bonding technique for mounting an optical device on a PLC (Planar Lightwave Circuit), and more particularly to a flip-chip bonding structure and method for improving the degree of the vertical alignment of an optical device relative to a PLC.
2. Description of the Related Art
Generally, the flip-chip bonding technique is one of various methods of bonding a semiconductor device onto a substrate. Different from the conventional wire-bonding or soldering method, in the flip-chip bonding method an array of metal pads are first formed on the surfaces of both the semiconductor device to be bonded and the substrate. Then, solder bumps are placed on either the metal pads of the substrate or the metal pads of the semiconductor device, or both. The semiconductor device is mounted in an upside-down manner over the substrate so that the metal pads or the solder bumps of the semiconductor device are aligned with the corresponding metal pads or the solder bumps of the substrate. Thereafter, solder material of the solder bumps is heated and re-flowed to physically bond the semiconductor device to the substrate.
As the optical characteristics of the optical device are sensitive to the vertical alignment of the optical device relative to the substrate, a small error in the vertical alignment drastically deteriorates the optical characteristics of the optical device. Therefore, in order to connect the optical device to an optical waveguide, such as the PLC, a precise vertical alignment of the optical device relative to the optical waveguide is required In order to align the optical device, such as a laser diode with the optical waveguide, a degree of precision of tolerance of less than ±1 &mgr;m is usually required.
FIG. 1
is a cross-sectional view of a conventional flip-chip bonding structure between an optical device and a PLC. As shown in
FIG. 1
, the PLC (Planar Lightwave Circuit)
10
comprises a silicon substrate
11
, a lower clad layer
12
, a core
13
, and an upper clad layer
14
. Furthermore, the PLC
10
comprises a metal electrode
15
and a solder bump
16
. The metal electrode
15
and the solder bump
16
are deposited successively on an etched surface of a designated area of the PLC
10
for mounting the optical device
20
. The designated area of the PLC
10
for mounting the optical device
20
is etched by a deep-etching method. Then the optical device
20
provided with solder pads is bonded to the PLC
10
by the flip-chip bonding method using the surface tension of the solder bump
16
of the PLC
10
. That is, after aligning the solder pad of the optical device
20
relative to the corresponding solder bump
16
located on the PLC
10
, the optical device
20
and the PLC
10
are heated so as to re-flow the solder bump
16
. As the solder bump
16
of the PLC
10
is re-flowed, the solder bump
16
assumes its most stable shape. The re-flowed solder bump
16
forms a bond between the optical device
20
and the PLC
10
.
However, in the aforementioned prior art, the depth of the etched area of the PLC
10
from the upper-clad layer
14
to the lower-clad layer
12
is approximately 30 &mgr;m. Therefore, it is difficult to adjust precisely the depth of the etched area of the PLC
10
within a range of the required tolerance in the optical device
20
. In addition, some error occurs in the thickness of the solder bump
16
formed by depositing a metal, which in turn deteriorates the optical characteristics. Furthermore, in the flip-chip bonding method, as the solder bumps of the PLC are re-flowed at high temperature and the optical device is bonded to the re-flowed solder bumps of the PLC, errors in the vertical alignment of the optical device relative to the PLC occur according to the bonding pressure and the re-flowing temperature, thereby seriously deteriorating the optical characteristics of the optical device further.
SUMMARY OF THE INVENTION
The present invention is related to a flip-chip bonding structure and its bonding method which has excellent bonding strength between an optical device and a PLC and avoids errors in the vertical alignment of the optical device relative to the PLC.
In accordance with one aspect of the present invention, the flip-chip bonding structure includes a semiconductor substrate; a lower-clad layer formed on the upper surface of the semiconductor substrate, wherein the lower-clad layer is depressed on a designated area for mounting an optical device: vertical-alignment structures formed on a part of the upper surface of the depressed area of the lower-clad layer for determining a vertical-alignment position of the optical device on the semiconductor substrate; electrodes formed on another part of the upper surface of the depressed area of the lower-clad layer; a solder bump formed on the upper surfaces of the electrodes; and, an optical device bonded to the substrate by a flip-chip bonding method using the solder bump.
Preferably, the thickness of the vertical alignment structure may be smaller than the total thickness of the electrode and the solder bump by over 0.5 &mgr;m.
Furthermore, preferably, the vertical alignment structure can be made of the same material as that of the lower clad layer.
More preferably, the vertical alignment structure may be made of silica.
In accordance with another aspect of the present invention, this invention provides a flip-chip bonding method comprising the steps of: forming a lower-clad layer and a core successively on a semiconductor substrate; etching the lower-clad layer and the core on a designated area for mounting an optical device so that the lower-clad layer is partially etched to leave the lower clad layer in a thickness that is necessary to align the optical device vertically on the semiconductor substrate; forming an upper-clad layer on the whole upper surface of the semiconductor substrate including the upper surface of the core and the etched surface of the lower-clad layer; forming steps on a part of the designated area for mounting the optical device by etching the upper-clad layer and the lower-clad layer on the designated area for mounting the optical device, wherein the steps serve as vertical-alignment structures; forming electrodes on the upper surface of the etched lower-clad layer of other parts of the designated area for mounting the optical device; depositing a solder bump on the upper surfaces of the electrodes; and, flip-chip bonding an optical device with bonding pads corresponding to the solder bump to the semiconductor substrate.
Preferably, the flip-chip bonding method can further comprise the step of forming an etching-stop layer on parts of the upper surface of the etched lower-clad layer of the designated area for mounting the optical device between the step of etching the lower-clad layer and the core on the designated area for mounting an optical device and the step of forming an upper-clad layer on the whole upper surface of the semiconductor substrate.
And, preferably, forming the steps can be carried out by etching the upper-clad layer and the lower-clad layer on the designated area for mounting the optical device by a deep dry-etching method using the etching-stop layer as an etching mask.
Furthermore, preferably, the etching-stop layer may be made of a material of whose selectivity to the lower clad layer is more than 10.
Moreover, preferably the lower-clad layer can be made of silica.
Preferably, the etching-stop layer can be made of aluminum.
Further, preferably, the step of depositing the solder bump can be carried out so that the total thickness of the electrode and the solder bump is greater than the thickness of the step by over 0.5 &mgr;m
Choi Duk-Yong
Kim Dong-Su
Lee Joo-Hoon
Cha & Reiter LLC
Cooke Colleen P.
Samsung Electronics Co,. Ltd.
Silverman Stanley S.
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