Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Flip chip
Reexamination Certificate
1999-08-11
2002-02-19
Williams, Alexander O. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Flip chip
C257S737000, C257S738000, C257S734000, C257S784000, C257S786000, C257S787000, C257S777000
Reexamination Certificate
active
06348738
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the field of semiconductor package fabrication techniques generally, and more specifically to methods for forming flip-chip-on-board assemblies.
BACKGROUND OF THE INVENTION
One of the main challenges in electronics design is the method used to form the mechanical and electrical bonds between a semiconductor integrated circuit (IC) and the chip carrier (or printed circuit board). Wire bonding and flip-chip are two of the most well known methods. The most common of these processes is wire bonding. In wire bonding, a plurality of bonding pads are located in a pattern on the top surface of the substrate, with the chip mounted in the center of the pattern of bonding pads and with the top surface of the chip facing away from the top surface of the substrate. Fine wires (which may be aluminum or gold wires) are connected between the contacts on the top surface of the chip and the contacts on the top surface of the substrate.
The most space-efficient method for joining an IC to a chip carrier is the flip-chip-on-board (FCOB) technique, also referred to as the flip-chip technique. In the flip-chip technique, the top surface of the IC chip has an array of electrical contact pads. A solder bump is formed on each of the contact pads. The chip carrier has a corresponding grid of contacts. The chip is flipped upside down so that the solder bumps mate with solder plating on the corresponding contacts on the chip carrier (hence the name “flip-chip”). The assembly is heated to reflow the solder plating on the chip carrier contacts. The solder plating, on the chip carrier contacts, reflows to join the IC chip and chip carrier. The footprint of the FCOB assembly is very close to the footprint of the IC chip alone.
Conventional flip-chip assemblies often have reliability problems due to thermal mismatch (differential thermal expansion). This differential thermal expansion may result from two different sources. First, the coefficient of thermal expansion (CTE) of the IC chip is typically 2.5×10
−6
/° C., whereas the CTE for the chip carrier is typically between 20 and 25×10
−6
/° C. Thus, the chip and chip carrier expand by different amounts at any given temperature. Second, the temperature within the chip may not be uniform, so that different parts of the chip expand at different rates. The differential thermal expansion in various portions of the chip and between the chip and the chip carrier apply stress to the solder joints, causing solder fatigue failures.
The most common technique for reducing the thermal mismatch problem is to position an organic-based encapsulant (underfill) between the IC chip and the chip carrier. The encapsulant bonds to both the IC chip and the chip carrier, constrains the thermal mismatch, and lowers the stress on the solder joints. The primary failure mechanism in FCOB assemblies that include the encapsulant is delamination at the interface between the active face of the IC chip and the encapsulant. Once adhesion between these two surfaces is lost, the solder joints are subjected directly to the stress of the thermal mismatch between the chip and the chip carrier. Electrical failure typically occurs rapidly after delamination.
To improve the reliability of FCOB assemblies sufficiently to make flip-chip technology more common, a method of preventing delamination between the encapsulant and the surface of the chip, the chip carrier, or both is desired.
SUMMARY OF THE INVENTION
The present invention is a method for forming a flip-chip on board (FCOB) assembly, and an FCOB assembly formed using the method. A plasma is applied to chemically modify a surface of the passivation layer of an integrated circuit (IC) chip, substantially without roughening the surface of the passivation layer. The IC chip is joined to a chip carrier via a plurality of solder bumps electrically connecting a plurality of contact pads on the IC chip to corresponding contacts on the chip carrier. A space is formed between the surface of the passivation layer and a surface of the chip carrier. An underfill encapsulant material is applied to fill the space. It is to be understood that both the foregoing general description and the following detailed description are exemplary, but are not restrictive, of the invention.
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Dery Jean
Egitto Frank D.
Matienzo Luis J.
Ouellet Charles
Ouellet Luc
Fraley, Esq. Lawrence R.
International Business Machines - Corporation
Ratner & Prestia
Williams Alexander O.
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