Flexible techniques for associating cache memories with...

Details Flexible techniques for associating cache memories with... Flexible techniques for associating cache memories with...

2007-04-10

2007-04-10

Verbrugge, Kevin (Department: 2189)

Electrical computers and digital processing systems: memory

Addressing combined with specific memory configuration or...

Addressing cache memories

C711S119000, C711S130000, C711S148000, C711S202000

Reexamination Certificate

active

11197899

ABSTRACT:
Caches are associated with processors, such multiple caches may be associated with multiple processors. This association may be different for different main memory address ranges. The techniques of the invention are flexible, as a system designer can choose how the caches are associated with processors and main memory banks, and the association between caches, processors, and main memory banks may be changed while the multiprocessor system is operating. Cache coherence may or may not be maintained. An effective address in an illustrative embodiment comprises an interest group and an associated address. The interest group is an index into a cache vector table and an entry into the cache vector table and the associated address is used to select one of the caches. This selection can be pseudo-random. Alternatively, in some applications, the cache vector table may be eliminated, with the interest group directly encoding the subset of caches to use.

REFERENCES:
patent: 5848432 (1998-12-01), Hotta et al.
patent: 5987569 (1999-11-01), Takahashi et al.
patent: 2002/0013877 (2002-01-01), Naya et al.

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