Electronic digital logic circuitry – Multifunctional or programmable – Array
Patent
1998-07-17
2000-02-22
Santamauro, Jon
Electronic digital logic circuitry
Multifunctional or programmable
Array
326 39, H03K 738, H03K 19177
Patent
active
060284463
ABSTRACT:
A programmable logic device (PLD) cell is used to construct a high density high performance programmable logic device (PLD). The PLD cell includes two programmable logic block cells. The PLD cell also includes an I/O cell and an input macrocell. In addition the PLD cell includes a sub-bank of a programmable output switch matrix bank and a sub-bank of a programmable input switch matrix bank. Each programmable logic block cell includes a multiplicity of product terms. At least one product term in the cluster is programmably available to the cluster. When the product term is disconnected from the cluster, the product term is used for control of the polarity of the logic macrocell output signal or asynchronous functions. Thus, the programmably connectable product term can be used for either synchronous or asynchronous operations. If the programmably connectable and disconnectable product term is connected to the product term cluster, the programmable logic block cell is used for synchronous operations. However, since each product term cluster is associated with a logic macrocell, the logic macrocell can be individually configured for asynchronous operation by simply disconnecting the appropriate product term from the product term cluster and using the product term for the desired asynchronous function. Thus, a single PLD built using the programmable logic block cells supports simultaneously synchronous and asynchronous operations.
REFERENCES:
patent: 3473160 (1969-10-01), Wahlstrom et al.
patent: 4012589 (1977-03-01), Reisinger
patent: 4124899 (1978-11-01), Birkner et al.
patent: 4321490 (1982-03-01), Bechdolt
patent: 4422072 (1983-12-01), Cavlan
patent: 4449063 (1984-05-01), Ohmichi et al.
patent: 4536859 (1985-08-01), Kamuro
patent: 4575794 (1986-03-01), Veneski et al.
patent: 4609986 (1986-09-01), Hartmann et al.
patent: 4653074 (1987-03-01), Griffin et al.
patent: 4668880 (1987-05-01), Shoji
patent: 4675673 (1987-06-01), Oliver
patent: 4677318 (1987-06-01), Veenstra
patent: 4713557 (1987-12-01), Carter
patent: 4717912 (1988-01-01), Harvey
patent: 4742252 (1988-05-01), Agarwal
patent: 4758746 (1988-07-01), Birkner
patent: 4771285 (1988-09-01), Agarwal et al.
patent: 4789951 (1988-12-01), Birkner et al.
patent: 4825414 (1989-04-01), Kawata
patent: 4871930 (1989-10-01), Wong et al.
patent: 4872137 (1989-10-01), Jennings, III
patent: 4878200 (1989-10-01), Asghar et al.
patent: 4879481 (1989-11-01), Pathak et al.
patent: 4885538 (1989-12-01), Hoenniger, III et al.
patent: 4903223 (1990-02-01), Norman et al.
patent: 4912342 (1990-03-01), Wong et al.
patent: 4912345 (1990-03-01), Steele et al.
patent: 4931671 (1990-06-01), Agarwal
patent: 4949339 (1990-08-01), Shimada et al.
patent: 4963768 (1990-10-01), Agarwal et al.
patent: 5015884 (1991-05-01), Agarwal et al.
patent: 5027011 (1991-06-01), Steele
patent: 5036473 (1991-07-01), Butts et al.
patent: 5046035 (1991-09-01), Jigour et al.
patent: 5055718 (1991-10-01), Galbraith et al.
patent: 5072136 (1991-12-01), Naghshineh
patent: 5083083 (1992-01-01), El-Ayat et al.
patent: 5121342 (1992-06-01), Szymborski et al.
patent: 5126950 (1992-06-01), Rees et al.
patent: 5130574 (1992-07-01), Shen et al.
patent: 5136188 (1992-08-01), Ha et al.
patent: 5151623 (1992-09-01), Agarwal
patent: 5191243 (1993-03-01), Shen et al.
patent: 5204555 (1993-04-01), Graham et al.
patent: 5204556 (1993-04-01), Shankar
patent: 5208833 (1993-05-01), Erhart et al.
patent: 5220214 (1993-06-01), Pedersen
patent: 5254886 (1993-10-01), El-Ayat et al.
patent: 5258668 (1993-11-01), Cliff et al.
patent: 5260610 (1993-11-01), Pedersen et al.
patent: 5260611 (1993-11-01), Cliff et al.
patent: 5317210 (1994-05-01), Patel
patent: 5347519 (1994-09-01), Cooke et al.
patent: 5359242 (1994-10-01), Veenstra
patent: 5377335 (1994-12-01), Keller et al.
patent: 5379382 (1995-01-01), Work et al.
patent: 5384499 (1995-01-01), Pedersen et al.
patent: 5384500 (1995-01-01), Hawes et al.
patent: 5451887 (1995-09-01), El-Avat et al.
patent: 5477165 (1995-12-01), El-Ayat et al.
patent: 5610534 (1997-03-01), Galbraith et al.
Altera User-Configurable Logic Databook, Sep. 1988, Rev. 2, pp. 10-19.
Brunvard, Erik, "Implementing Self-Timed Systems with FPGAs", FPGAs, 1991 Abingdon EE&CS Books.
Burksy, Dave, "Clock-Free Macrocells Simplify Asynchronous System Design", Electronic Design, Jul. 14, 1988.
Bursky, Dave, "Design Bus Interfaces, Peripherals with Programmable-Logic Chip", Electronic Design, Aug. 20, 1987.
Choi, Bong-Rak, et al., "An Improved Hardware Implementation of the Fault-Tolerant Clock Synchronization Algorithm for Large Multiprocessor Sysatems", IEEE Transactions on Computers, vol. 39, No. 3, Mar. 1990.
Creamer, David, "MAX Architecture Addresses Both `Gate Intensive` and `Register Intensive` Applications", WESCON/90 Conference Record, Nov. 15-17, 1988.
El-Ayat, Khaled A., "A CMOS Electrically Configurable Gate Array", IEEE Journal of Solid-State Circuits, vol. 24, No. 2, Apr. 1989.
Faria, Donald, "MAX EPLD Family: PAL Speed to FPGA Density", WESCON/90 Conference Record, Nov. 13-15 1990.
Gupta, Anil, "A User Configurable Gate Array Using CMOS-EPROM Technology", IEEE 1990 Custom Integrated Circuits Conference, 1990.
Noore, Afzel, "Microcontroller Compatible Clock Chip Design Using Field Programmable Gate Array", IEEE Transcations on Consumer Electronics, Aug. 1991.
Wong, Sau C., "A 5000-Gate CMOS EPLD with Multiple Logic and Interconnect Arrays", IEEE 1989 Custom Integrated Circuits Conference, 1989.
Stan Kopec et al., "Obtaining 70MHz Performance in the MAX Architecture", Electronic Engineering, vol. 63, No. 773, May 1991, pp. 69,70,72,74.
Doug Connor, "PLD Architectures Require Scrutiny", EDN Electrical Design News, vol. 34, No. 20, Sep. 28, 1989, pp. 91,93,94,96,98,100.
Steve Landry, "Application-Specific IC's Relying on RAM, Implement Almost any Logic Function", Electronic Design, vol. 33, No. 25, Oct. 1985, pp. 123-128, 130.
"Introduction to pLSI and ispLSI", pLSI and ispLSI Databook&Handbook, Lattice Semiconductor Corp., (undated), pp. 1-1 through 1-8.
"pLSI 1032 programmable Large Scale Integration", Rev. A., Lattice Semiconductor Corp., Jan. 1992, pp. 2-1 through 2-29.
"EPM7032 EPLD, High-Performance 32-Macrocell Device", Data Sheet, Altera Corp., Ver. 1, Dec. 1991, pp. 1-15.
Om P. Agarwal, "AMD's Next Generation MACH.TM. 3xx/4xx Family Breaks New PLD Density/Speed Barrier", Conference Record, Wescon 92, Nov. 1992, pp. 100-106.
Raymond Leung et al., "A 7.5 ns 350m W BiCMOS PAL.RTM.-type Device", Proceedings of the 1989 IEEE Custom Integrated Circuits Conference, May 1989, pp. 5.6.1-5.6.4.
Agrawal Om P.
Ilgenstein Kerry A.
Advanced Micro Devices , Inc.
Kwok Edward C.
Roseen Richard
Santamauro Jon
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