Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2001-08-03
2004-02-17
Siek, Vuthe (Department: 2818)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06694496
ABSTRACT:
Related applications, which are incorporated herein by reference, are:
IMPROVED APPARATUS AND METHOD FOR MULTI-THREADED SIGNAL PROCESSING
Ser. No. 09/492,634, filed on Jan. 27, 2000.
TECHNICAL FIELD
The present claimed invention relates to the field of telecommunication. In particular, the present claimed invention relates to an apparatus and a method for descrambling data.
BACKGROUND ART
Electronic communication devices, such as cell phones, base stations, global positioning systems (GPS) are ubiquitous in everyday business and personal use. IN order to transmit information between two communication devices, they have to know that they exist. Several different methods identify how a first communication device can determine if a second communication device is trying to transmit to them. One such method is to detect a known code sequence transmitted by the second communication device on a specific channel at an unknown offset. By scanning for the known code sequence at different offsets, the first communication device can eventually obtain a match between its internally generated codes and the input data from the second communication device on the specific channel.
The process of searching input data for known codes is very computationally intensive. Because the known code sequence is a long sequence, the amount of computation that must be performed to span the known code sequence can be extensive. However the computations are somewhat repetitive and may be inefficient. Additionally, part of the known code sequence involves several possible hypotheses. This means that multiple hypotheses will have to be checked to determine if a good correlation exists, and thus more computations are required.
Furthermore, because the known channel will be searched continuously to monitor for new transmissions from other communication devices, the computation for the known code sequence can occur ad infinitum. Due to the constant and complicated computations involved, a need also exists to overcome inefficiencies with searching data for a known sequence.
In particular, power is critical in many data processing applications. And computational operations require power to be performed. Thus a need arises to overcome the limitation of excessive quantity of data computations used to search for a known sequence on a channel in order to conserve power.
The search for a new transmission is necessary to establish a link between the two communication devices. Only after a link is established can user data be transmitted between the two communication devices. The computations for the known code sequence are extensive and complicated, and thus consume a substantial amount of time. Yet performance metrics dictate that the search be conducted in a short amount of time. Consequently, a need arises for a method and apparatus to overcome the time limitations for searching a channel for the known sequence.
SUMMARY OF THE INVENTION
The present invention provides a method and apparatus that overcomes inefficiencies with the complicated and continuous computations to check a channel for a known sequence. Furthermore, the present invention overcomes the limitation of excessive quantity of data computations used to search for a known sequence on a channel in order to conserve power. Lastly, the present invention overcomes the time limitations for performing the search.
A first embodiment of the present invention provides an architecture and method for flexible preamble processing. In particular, the preamble-processing engine detects a code sequence in input, where the code sequence is a sum of a first code sequence and a second code sequence. The preamble-processing engine includes a data input line, a code input line, a despreader, and a plurality of memory registers. The code input selectively receives the first code sequence or the second code sequence, the first code sequence having a period longer than a period for the second code sequence. The despreader is coupled to the data input line and the code input line. The despreader producing a despread result between the first code sequence and the input data. Lastly, the plurality of memory registers, which are coupled to the despreader, each stores only a portion of the despread results.
These and other objects and advantages of the present invention will become apparent to those of ordinary skill in the art after having read the following detailed description of the preferred embodiments, which are also illustrated in the various drawing figures.
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patent: 6389000 (2002-05-01), Jou
patent: 2001/0048714 (2001-12-01), Jha
Balasubramonian Venugopal
Goslin Gregory R.
Darby & Darby
Morphics Technology Inc.
Siek Vuthe
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