Flexible parity generation circuit for intermittently generating

Details Flexible parity generation circuit for intermittently generating Flexible parity generation circuit for intermittently generating

1995-03-10

1995-11-21

Beausoliel, Jr., Robert W.

Excavating

371 404, 371 492, 39518207, 39518308, 395441, H03M 1300, G06F 1100, G06F 1110

Patent

active

054695660

ABSTRACT:
A redundant array computer system having a high-speed CPU bus and lower-speed I/O buses, in which parity blocks are generated for a plurality of data blocks from multiple CPU bus logical channels in a randomly-interleaved manner to provide enhanced I/O transfer rates. For example, such a system may have two channels for processing two sets of data. The parity generation technique employs a switching circuit to switch channels on the CPU bus between the first set and the second set, generating parity information that can be transferred independently over two I/O buses. The parity generation technique achieves an effective I/O bus transfer rate more closely matched to the speed of the CPU bus. The invention shares a single XOR gate and related support circuitry between multiple logical channels by providing a configurable electronic memory, thus achieving economies in implementation. For certain system applications, it may be desirable to utilize the RAM as a large, unified FIFO. Thus, the system can be adapted to generate parity information for very large blocks of data in a single channel.

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Hou et al "Balancing I/O Response Time and Disk Rebuild Time in a RAID 5 Disk array" 1993 IEEE pp. 70-79.

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