Electronic digital logic circuitry – Multifunctional or programmable – Having details of setting or programming of interconnections...
Reexamination Certificate
2009-10-08
2011-11-15
Ismail, Shawki S (Department: 2819)
Electronic digital logic circuitry
Multifunctional or programmable
Having details of setting or programming of interconnections...
C326S037000, C326S039000, C326S040000, C326S041000, C326S101000, C712S220000, C712S221000, C712S233000, C712S235000, C712S241000
Reexamination Certificate
active
08058896
ABSTRACT:
A programming interface device for a programmable logic circuit comprises a series of parallel logic block chains each having first and second connection means, the first and second connection means being disposed at opposite ends of each chain. The programming interface device comprises first and second interfacing means for interfacing with the first and second connection means of each logic block chain, respectively and at least one programming circuit, each programming circuit arranged to configure a plurality of serially connected logic blocks. Finally, the programming interface comprises programmable connection means for connecting the connection means of each logic block chain to either the connection means of another logic block chain or directly to one of the at least one programming circuits, such that the parallel logic block chains can be configured in parallel, series or in any combination thereof.
REFERENCES:
patent: 2003/0055861 (2003-03-01), Lai et al.
patent: 2003/0184339 (2003-10-01), Ikeda et al.
patent: 2007/0113054 (2007-05-01), Guibert et al.
European Search Report issued in European Patent Application No. EP 08166153.0-1243, dated Apr. 24, 2009.
R. Cucchiara et al., “Reconfiguring the boundaries of a mesh-connected array of processors with run-time programmable logic,” Microprocessors and Microsystems, vol. 17, No. 2, 1993, pp. 67-73.
Deeley Simon
Stansfield Anthony
Ismail Shawki S
McDermott Will & Emery LLP
Panasonic Corporation
Tabler Matthew C
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