Flexible latency in flash memory

Details Flexible latency in flash memory Flexible latency in flash memory

2007-01-02

2007-01-02

Elms, Richard (Department: 2824)

Static information storage and retrieval

Addressing

Sync/clocking

C365S221000, C365S189050, C365S189011

Reexamination Certificate

active

11135231

ABSTRACT:
A method of reading data in and outputting data from a memory structure includes a buffer. In the present method, first read operation is undertaken to read a first set of data in the memory structure and provide data of the first set of data to the buffer, using an output clock. A first output operation is undertaken providing data read in the first read operation from the buffer, and a second read operation is undertaken to read a second set of data in the memory structure and provide data of the second set of data to the buffer, using the output clock. A second output operation is undertaken providing data read in the second read operation from the buffer. In the event that the completion of the first output operation would occur prior to the completion of the provision of the data of the second set of data to the buffer, a flexible time delay approach is undertaken so that, between the completion of the first output operation and the beginning of the second output operation, the minimum number of latencies are added as needed to insure that the provision of the data of the second set of data to the buffer is completed prior to the initiation of the second output operation.

REFERENCES:
patent: 6038169 (2000-03-01), Ogura et al.
patent: 7042795 (2006-05-01), Lee et al.

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