Electrical computers and digital data processing systems: input/ – Input/output data processing – Input/output command process
Reexamination Certificate
2000-08-21
2004-02-17
Gaffin, Jeffrey (Department: 2182)
Electrical computers and digital data processing systems: input/
Input/output data processing
Input/output command process
C710S033000, C710S065000
Reexamination Certificate
active
06694382
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to electronics, and more particularly, to input-output (I/O) devices.
BACKGROUND OF THE INVENTION
Input/output (I/O) devices are an essential component in computing structures. I/O devices provide a means for signals from sensors or other devices to be sent to a processor or memory within the computing structure. I/O devices also provide a way for a computing structure to communicate with other processors or to a human user.
In highly complex computing environments it may be necessary to process data from many sources. For instance, in an avionics environment data from dozens of sensors must be input to a processor. This sensor data may be analog or discrete in format and is required to be converted to digital format at different rates. In addition, changes to the number or type of sensor data may be required from time to time. Typically, I/O devices place data into only a single data location. I/O controllers have been constructed that allow data transfer to multiple locations, but they typically use more complex dedicated hardware or slower software implementations to do so. Some software implementations require thousands of lines of code, which takes up valuable memory space and is expensive to develop. Furthermore, transferring and routing of data has typically been performed by separate functions from those used for entry or exit of data from a user.
A flexible input/output (I/O) subsystem is therefore desired to accommodate growth potential in current product types, as well as to promote re-use of the I/O capabilities as part of a more re-usable architecture. Required capabilities include the need to make input data available to a local user (e.g., a processor), and also to autonomously forward such data to other users (e.g., redundant lanes or channels, or to other external users for which the I/O subsystem may be acting as a data concentrator). Other needed functions include output of locally-generated (e.g., computed) data, queuing of data for order-dependent temporary storage, and the capability of providing immediate activations or alerts (such as interrupts) for specific data parameters. Low latency time data transfers are required for very high rate closed-loop control systems.
The I/O subsystem must further be of a simple enough nature and implementation to allow it to be analyzed and certified for highly critical applications in a cost-effective manner. Such applications may include the most critical aspects of flight control, such as automatic landing in near-zero visibility and Fly-By-Wire. Certification requirements include not only the need to ensure that the design is correct (i.e., no “generic errors”), but also to perform failure detection as necessary to ensure that an accumulation of random failures cannot produce a hazard. Availability is also an important parameter for such systems, further suggesting the need for small, simple approaches to I/O. The desired flexibility and growth have typically been in conflict with the need for simple mechanisms that are appropriate for certification of highly critical systems.
Another related issue is testing of an I/O device to ensure that the device is accurately and consistently relaying data signals as intended. Testing of an I/O device should include the signal-producing elements and the signal-receiving elements, including the memories used for look-up and storage. Such testing should also include the Interconnection among these Items. Such testing can be complicated by the enormous number of possible operations and transfers that may be performed. Furthermore, testing must check not only intended transfers, but also must recognize any unintended transfers that may occur due to a failure.
It is therefore an object of the invention to provide an I/O mechanism that is simple in construction and can handle a large amount of transfers.
It is another object of the invention to provide an I/O mechanism that can be quickly tested with a high degree of confidence in the testing results.
It is still another object of the invention to provide an I/O device that may be used to prevent corrupted data from being transferred to other components in a data processing environment.
It is yet another object of the invention to provide an I/O device that may be used in a modular processing architecture.
It is still another object of the invention to provide an I/O device that may be used to prevent the transfer of corrupt data in a redundant computing system.
A feature of the invention is an input/output mechanism that receives a plurality of data signals and transfers the signals to one or more output devices according to directions contained in a look-up table.
An advantage of the invention is that an input/output device having a simple architecture may be configured to transfer a wide variety of inputs and outputs in any desired combination.
SUMMARY OF THE INVENTION
The invention provides a data transfer mechanism for directing data signals from signal-producing elements to signal-receiving elements. The data transfer mechanism includes a plurality of input ports, with each input port being connected to a signal-producing element, and a plurality of output ports, with each output port being connected to a signal-receiving element. Each data signal that enters the data transfer mechanism through one of the plurality of input ports has data identification information associated therewith. The data transfer mechanism directs the data signal to at least one of the plurality of output ports according to the data identification information associated with the data signal.
In another aspect of the invention, a method of selectively transferring data signals between signal-producing elements and signal-receiving elements is disclosed. According to the invention, a first data transfer mechanism is provided that has a plurality of input ports and a plurality of output ports. Each input port is connected to a signal-producing element and each output port is connected to a signal-receiving element. A data signal is accepted from a first signal-producing element. A look-up table, which is stored in a memory, is accessed to determine what should be done with the data signal. The data signal is directed to at least one of the signal-receiving elements through at least one of the output ports according to information contained in the look-up table.
In another aspect of the invention, a method of testing the accuracy of transfers performed by a data transfer mechanism is described. The data transfer mechanism has a plurality of input ports attached to signal-producing elements and a plurality of output ports attached to signal-receiving elements. According to the method, preselected instructions, stored in a memory, are provided that direct the flow of data signals from the input ports to predetermined output ports. A test signal is generated that is representative in format to each data signal that is received by each input device under normal conditions. The test signals are fed through the input ports that are normally connected to the input devices such that the test signals fed through each input port are representative in format to the data signals received by each input port under normal conditions. Each output port is checked to ensure that the test signals are routed according to the preselected instructions.
According to still another aspect of the invention, an apparatus for transferring data signals is disclosed. A first input/output (I/O) device has a first plurality of input ports attached to signal-producing elements and a first plurality of output ports attached to signal-receiving elements. The first I/O device is connected to a data bus that transfers data signals between all components connected thereto. The data bus is connected to a processor. Each data signal entering the first data transfer mechanism through the data bus and the first plurality of input ports has a data identification information associated therewith. A first memory is connected to the data bus. The
Aull Ronald W.
Kovalan Mark A.
Persick John L.
Wiscons Bryon L.
Eppele Kyle
Gaffin Jeffrey
Jenson Nathan O.
Rockwell Collins, Inc.
Schneider Joshua D.
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