Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2002-11-06
2004-11-30
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
06826741
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to peripheral routing resources in an electronic device, particularly with respect to programmable logic devices.
2. Description of Related Art
Programmable logic devices (“PLDs”) (also sometimes referred to as CPLDs, PALs, PLAs, FPLAs, EPLDs, EEPLDs, LCAs, FPGAs, or by other names), are well-known integrated circuits that provide the advantages of fixed integrated circuits with the flexibility of custom integrated circuits. Such devices are well known in the art and typically provide an “off the shelf” device having at least a portion that can be electrically programmed to meet a user's specific needs. Application specific integrated circuits (“ASICs”) have traditionally been fixed integrated circuits, however, it is possible to provide an ASIC that has a portion or portions that are programmable; thus, it is possible for an integrated circuit device to have qualities of both an ASIC and a PLD. The term PLD as used herein will be considered broad enough to include such devices.
PLDs typically include blocks of logic elements, sometimes referred to as logic array blocks (“LABs”; also referred to by other names, e.g., “configurable logic blocks,” or “CLBs”). Logic elements (“LEs”, also referred to by other names, e.g., “logic cells”) may include a look-up table (LUT) or product term, carry-out chain, register, and other elements. LABs (comprising multiple LEs) may be connected to horizontal and vertical conductors that may or may not extend the length of the PLD's core and connect to input/out (“I/O”) blocks.
I/O blocks typically include buffers, registers, and may include other elements. I/O blocks (sometimes referred by other labels, e.g., I/O elements, or “IOEs” the term “I/O block” may also refer to groups of I/O elements—I/O buffers, I/O cells, “IOs”, etc.) perform I/O functions that may include, for example, implementing I/O standards (e.g. LVTTL, LVCMOS, 2.5V, 1.8V, etc.) that define the requirements for transmitting/receiving a logical “1” or “0.” I/O functions also may include, for example, buffering data, routing data to and from the various LEs of the PLD, the demultiplexing of signals, and other functions. I/O blocks and other circuitry such as, for example, phase locked loops (PLLs), delay locked loops (DLLs), and other clock circuitry may benefit from being proximate to the periphery and pins of the device.
An I/O bus typically provides routing capability between an integrated circuit's core logic and its I/O circuitry. An integrated circuit's I/O circuitry is typically arranged on a periphery of the chip, proximate to the device's pins. In one example of past I/O buses, routing is provided into the core on the same side of the device that a signal is received via the I/O circuitry. The core routing is then used to deliver the signal to its destination or destinations. Similarly, if core logic needs to deliver a signal to the I/O circuitry, it is routed through the core routing to the I/O bus lines on the side of the device where the destination I/O circuitry resides. In an example of such a past architecture, a particular I/O bus line is dedicated to provide either core-to-I/O routing or I/O-to-core routing, but not both.
As core density and complexity increases and as the volume of signals processed by a device grows, it is increasingly cumbersome to rely on core routing to distribute a signals that must travel greater distances than the typical core route. Furthermore, even within the core, it may be cumbersome to route signals over core routing between two points whose distance apart presents a signal route greater than that typical of other core routes, particularly given that core line lengths are typically optimized for shorter routes. Thus, I/O routing resources are needed that can be utilized by core circuitry to deliver signals over longer routes within the core for which existing core routing is not optimized.
If I/O routing resources are to be relied on for lengthy signal routes, then it is increasingly important that the length of individual I/O lines is speed-optimized long routes. Thus, there is a need for an I/O bus architecture that accommodates the line length necessary to achieve such optimization in a particular integrated circuit. Because the optimal line length will vary depending on many factors related to the design and fabrication of a particular device, there is a need for an architecture that can adapt to a range of optimal line lengths.
As device complexity and signal volume grow, it is also increasingly necessary to provide highly flexible routing in the I/O bus so that multiple I/O bus routing options are readily accessible from a variety of locations on the device.
There is also a need to accommodate increasing fanout of signals routed on an I/O bus (i.e., a given signal is delivered to many locations). As fanout increases, there is a need to provide I/O bus routing that can handle increasing fanout while minimizing the added capacitance and other loading such fanout can cause.
If an I/O bus architecture forms a bus around the entire perimeter of a device, it may be difficult to design the device such that all I/O routing lines are of the same logical length. In particular, if the desired number of I/O blocks around a chip's periphery is not an integral multiple of the logical length of optimized lines, then it is difficult to form a continuous loop of connected bus lines without one or more of the lines being of a length different than the optimized length. This is undesirable not only because some lines are then not optimized, but also because creating routing algorithms is more difficult if the lines relied on are of inconsistent length. Thus, there is a need for a layout of lines that can accommodate a consistent logical line length whether or not the number of I/O blocks is an integral multiple of the desired logical line length.
SUMMARY OF THE INVENTION
In one aspect, the present invention provides flexible routing resources comprising an arrangement of staggered line segments on a periphery of an electronic device. In another aspect, peripheral bus lines are coupled to receive signals from and provide signals to other bus lines, core routing, and I/O circuitry, thus facilitating the use of the I/O bus for a variety of routes that may include I/O-to-core, core-to-I/O, I/O-to-I/O and core-to-core routes. In another aspect, a length of peripheral bus lines is optimized for speed over long signal routes with high fanout. In another aspect, the loading effects of high fanout are minimized by using a plurality of tapping buffers to couple lines to both core routing and to I/O circuitry. In another aspect, a spiraling technique is provided that allows a continuous bus having lines of consistent optimal length whether or not the number of I/O blocks is an integral multiple of the logical length of optimized lines.
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“XC4000E and XC4000X Series Field programmable Gate Arrays”, XILINX, product specification Version 1.6 May 14, 1999, 9 pgs.
“Virtex™ -E 1.8 V Field Programmable Gate Arrays”, XILINX, product specification v2-2, 7/23, 2001, 7 pgs.
Kluwer Academic Publishers, Vaughn Betz, Jonathan Rose, Alexander Marquardt,Architecture and CAD for Deep-Submicron FPGAs, Chapter 2.1 (pp. 11-18), Chapter 4 (pp. 63-103), Chapter 5 (pp. 105-126), and Chapter 7 (pp. 151-190), (Mar. 1999).
Betz Vaughn
Chan Michael
Jefferson David
Johnson Brian D.
Lee Andy L.
Altera Corporation
Lin Sun James
Siek Vuthe
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