Flexible DRAM array

Details Flexible DRAM array Flexible DRAM array

1994-12-14

1998-03-03

Nguyen, Tan T.

Static information storage and retrieval

Read/write circuit

Including level shift or pull-up circuit

365203, 36523006, G11C 700

Patent

active

057242860

ABSTRACT:
A DRAM array comprised of plural wordlines and plural bitlines, bit charge storage capacitors associated with the bitlines and wordlines, cell access field effect transistors (FETs) having their gates connected to the wordlines and their source-drain circuits connected between the bitlines and the charge storage cells, for enabling reading or writing data from or to the charge storage capacitors, and programmable addressing apparatus for causing the wordlines, once addressed, to selectively enable either one or more than one cell access FET, whereby data can be selectively read from or written to one or more than one charge storage capacitor.

REFERENCES:
patent: 4788664 (1988-11-01), Tobita
patent: 4896297 (1990-01-01), Miyatake et al.
patent: 5073731 (1991-12-01), Oh
patent: 5202855 (1993-04-01), Morton
patent: 5214602 (1993-05-01), Lines
patent: 5253202 (1993-10-01), Brunner et al.
patent: 5255224 (1993-10-01), Galbi et al.
patent: 5274592 (1993-12-01), Sueoka et al.
patent: 5287325 (1994-02-01), Morita
patent: 5297104 (1994-03-01), Nakashima
patent: 5373479 (1994-12-01), Noda

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