Flexible delay cell architecture

Details Flexible delay cell architecture Flexible delay cell architecture

2011-01-04

2011-01-04

Cho, James H. (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Array

C326S093000, C326S038000

Reexamination Certificate

active

07863931

ABSTRACT:
A flexible delay cell architecture and related methods are provided that may be used, for example, with input/output (I/O) blocks of a programmable logic device (PLD). In one implementation, a PLD includes a delay cell comprising a plurality of delay elements. The delay elements are adapted to delay an input signal to provide an output signal according to a delay setting corresponding to a number of the delay elements. The PLD also includes a register adapted to store the delay setting. The PLD further includes an edge monitor adapted to signal whether an edge transition of the output signal has occurred during a time window. In addition, the PLD includes logic adapted to adjust the delay setting stored by the register in response to the edge monitor signaling the edge transition.

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