Flexible configuration logic array block for programmable logic

Details Flexible configuration logic array block for programmable logic Flexible configuration logic array block for programmable logic

1993-04-19

1994-08-23

Westin, Edward P.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

34082583, 3074651, H03K 19173

Patent

active

053410440

ABSTRACT:
A programmable logic device has a number of dedicated global control input lines which interface directly with individual building blocks known as logic array blocks. These lines can be used for clocks, presets, clears, or output-enables. Other logic signal lines from the centrally located global interconnect array are selected through an array of multiplexers and then interface with the logic array block. A configuration array of multiplexers in the logic array block selects from among these inputs, generating local control input signals, the final functions of which are decided by further multiplexing at the macrocell level within the logic array block.

REFERENCES:
patent: 4617479 (1986-10-01), Hartmann
patent: 4779229 (1988-10-01), Agrawal
patent: 5079451 (1992-01-01), Gudger
patent: 5225719 (1993-07-01), Agrawal
patent: 5268598 (1993-12-01), Pederson
Altera Corporation Sep. 1991 Data Book, pp. 1-34.

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