Electricity: conductors and insulators – Conduits – cables or conductors – Preformed panel circuit arrangement
Reexamination Certificate
1998-08-12
2001-04-03
Gaffin, Jeffrey (Department: 2841)
Electricity: conductors and insulators
Conduits, cables or conductors
Preformed panel circuit arrangement
C174S262000, C174S266000
Reexamination Certificate
active
06211468
ABSTRACT:
BACKGROUND
The disclosures herein relate generally to flexible circuits and more particularly to conductive vias provided to interconnect circuit traces on opposite side of the circuit substrate.
The current trend in packages for integrated circuits is to use automated forms of lead bonding such as tape automated bonding (TAB) and flip chip techniques as opposed to the more traditional method of wire bonding. This trend stems from the requirement for increased number of inputs and outputs (I/O) in a package as well as improved reliability, enhanced electrical signal performance and increased yields. To meet these demands, flip-chip packages and multi-chip modules employing flip-chip bonding techniques are beginning to replace more conventional packaging architectures.
Double sided circuits typically are fabricated by forming a conductive pattern on opposing sides of a planar dielectric material and interconnecting the opposing conductive layers with conductive vias. Various processes and techniques, generally involving conventional photolithographic methods, are used to form the conductive circuit patterns on double sided circuits. Photolithographic techniques for forming conductive circuits are explained and well documented in electronic packaging handbooks and in patent literature, e.g. U.S. Pat. No. 5,227,008. Various well-known methods are also used to form vias in the dielectric which separates the conductive layers. Common via forming methods include mechanically punching, drilling, laser ablation, chemical (wet) or plasma etching. These methods have been commonly used to form straight, vertical sidewalls, which terminate at a 90-degree angle with the opposite surfaces of the dielectric material as well as low aspect ratio tapered wall vias. After the via holes are formed in the dielectric, additional processing steps take place to electrically connect the circuit patterns on either side of the dielectric through the via holes. Thus, the vias serve as conductive feedthroughs or conductive through holes.
Although the above mentioned techniques as well as many other methods are available to create the dielectric holes which serve as the openings for the conductive feedthroughs between layers, these methods create vias which have one or more limitations. Foremost among the limitations associated with prevailing via types is the shape of the vias. Common via shapes, with high aspect ratios, serve to both generate and accelerate the accumulation and concentration of the forces which induce stress into the surrounding circuit features. This induced stress often causes premature brittle cracking and failure of the metallic conductors and or causes the conductors to delaminate from the dielectric. Many conventional methods have been tried in the efforts to eliminate these types of stress failures. Some of these methods are described or referenced in U.S. Pat. No. 5,288,541.
Although many methods exist which attempt to eliminate stress failures, they have had only limited success at doing so. As mentioned, the stress generating and stress concentrating nature of conventional vias are due to the problematic shape of the vias. Conventional via shapes do not successfully alleviate the effects of Z-axis movement of the materials used in the construction of the vias. Movement in the Z-direction is distinctly different for all of the materials used in the construction of double sided circuits and vias, and this mismatch of the physical properties of these materials is the source of the stress, often severe, which in turn causes the circuit to fail.
Copper is the most common conductive metal used as the electrical feedthrough in the via. Copper has a well known thermal coefficient of expansion of 17 ppm/°C. In the construction of double sided circuits, copper may be applied (laminated, vapor deposited, etc.) to any number of different types of dielectric materials. Among the more common dielectric materials are polyimide, FR4, BT resin, etc. Polyimide is typical of these dielectric materials in that there are many different types of polyimide which can be either flexible or rigid. Z-axis values of the thermal coefficient of expansion of the commercially available polyimides used to construct double sided circuits are in the ranges of 120 to 140 ppm/°C. Therefore, this substantial difference in the thermal coefficients of expansion of copper and polyimide can cause extremely high stresses in and around the via, especially at the 90 degree angle where the via sidewall intersects the opposite surfaces of the dielectric material. These stresses are cyclic and extremely high in value relative to the tensile strength of the copper. The cyclic nature of the stresses serves to work harden the copper at a point at which the tensile forces in the copper is at a maximum. Over time, often a relatively short time, the tensile strength of the copper decreases due to work hardening. Finally, the copper cracks and ruptures at the 90 degree angle and the circuit fails mechanically and electrically.
Although mismatches of thermal expansion coefficients in the Z direction are the source of much stress associated with conductive vias, there are also many other causes of stress. Some of these stresses are caused by differences in hygroscopic expansion between the metal and the organic substrate, and differences in expansion caused by solvents, organic or otherwise, used in the manufacture, processing, or handling of multilayer circuits, etc.
The many causes of stress in a circuit having vias with conductive feedthroughs, and the poor ability of conventional double sided circuits with conducive vias to effectively limit the effects of the stresses, have therefore created a need for a multilayer circuit, with interconnecting vias which is inherently resistant to the deleterious effects of Z-axis movement and associated stress.
U.S. Pat. No. 5,166,097 discloses a method for making conductive feedthroughs in silicon wafer interposers utilized in silicon wafer multi-chip modules. The feedthroughs are in a silicon wafer substrate rather than the polymeric substrate of a flexible circuit. Due to the conductivity of doped silicone, the feedthroughs must be electrically isolated from each other by applying a layer of dielectric material within the feedthroughs prior to metallizing them. The inherent dielectric properties of a polymeric flexible circuit substrate preclude the need to electrically isolate the feedthroughs. Furthermore, the feedthroughs are fabricated with an anisotropic etching process called orientation-dependent-etching (ODE) such that a high aspect ratio of 400:1 is attained. This type of anisotropic wet etching process relies on the crystal structure of the silicon wafer to provide for such a high aspect ratio. Wet etching of feedthroughs in polymeric flexible circuit substrates are anisotropic but the polymeric material does not permit aspect rations attainable with an ODE etching process.
Therefore, what is needed is a flexible circuit suitable for flip chip and wire bond applications having high I/O's. Moreover, the need for methods of manufacturing a flexible circuit which is capable of meeting increased I/O requirements, at an economical yet reliable fashion, also continues to exist.
SUMMARY
One embodiment, accordingly, provides an apparatus and a method for forming an electrically conductive via in a dielectric substrate which separates opposing conductive layers of a circuit. The conductive vias provide a feedthrough to link the opposing conductive layers and conduct an electrical signal from one conductive layer to the other. To this end, a flexible circuit includes a flexible non-conductive substrate having a first surface and a second surface. A first electrically conductive trace is provided on the first surface and a second electrically conductive trace is provided on the second surface. A passage extends through the substrate from the first trace to the second trace. The passage has an hourglass shaped sidewall which substantially converges between the first and second surfaces,
3M Innovative Properties Company
Cuneo Kamand
Fonseca Darla P.
Gaffin Jeffrey
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