Flexible cache architecture using modular arrays

Details Flexible cache architecture using modular arrays Flexible cache architecture using modular arrays

2000-02-18

2002-12-10

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

06493855

ABSTRACT:

TECHNICAL FIELD
This invention relates in general to memory architecture, and in particular to a flexible memory architecture implementation that can be easily adapted in response to compositional changes in the die of a chip.
BACKGROUND
Computer systems may employ a multi-level hierarchy of memory, with relatively fast, expensive but limited-capacity memory at the highest level of the hierarchy and proceeding to relatively slower, lower cost but higher-capacity memory at the lowest level of the hierarchy. The hierarchy may include a relatively small, fast memory called a cache, either physically integrated within a processor or mounted physically close to the processor for speed. The computer system may employ separate instruction caches (“I-caches”) and data caches (“D-caches”). In addition, the computer system may use multiple levels of caches. The use of a cache is generally transparent to a computer program at the instruction level and can thus be added to a computer architecture without changing the instruction set or requiring modification to existing programs.
Turning to
FIG. 1
, an integrated circuit (chip) design of the prior art for a microprocessor is shown. As shown in
FIG. 1
, the design for chip
100
includes a non-memory block, shown as CPU core
40
, which may include such components as an ALU for integer execution, a floating point execution unit, and lower level caches (e.g., level 1 cache), as well as other various components. Therefore, as used herein a non-memory block may refer to a non-memory portion of an integrated circuit, such as the CPU core of a microprocessor chip. Furthermore, such a non-memory block may comprise several smaller, non-memory components therein, such as an ALU, floating point execution unit, and other non-memory components of a microprocessor chip. As processor speeds increase and greater performance is required for processors, it becomes increasingly important for larger caches to be implemented for a processor. As described above, cache memory is typically capable of being accessed by a processor very quickly. Thus, the more data contained in cache, the more instructions a processor can satisfy quickly by accessing the fast cache. That is, generally, the larger the cache implemented for a processor, the better the performance of such processor. Therefore, processor chips of the prior art commonly implement large cache structures. For example, as shown in
FIG. 1
, a higher level memory (e.g., level 2 cache) is implemented on the processor chip in memory blocks
10
,
20
, and
30
. It is common in prior art designs for such additional memory to consume half (or even more) of the surface area of the die for a chip.
In memory architecture (or memory organization) of the prior art, memory blocks, such as memory blocks
10
,
20
, and
30
, are typically implemented in relatively large, rectangular (or square) blocks. For example, memory blocks are commonly implemented having 256 by 256 memory cells, 512 by 512 memory cells, or 1024 by 1024 memory cells. Such memory blocks of the prior art are typically limited to being rectangular blocks. Each of the blocks
10
,
20
, and
30
typically have an independent decode and input/output (I/O) circuits. For example, block
10
may have a decode circuitry
12
and I/O circuitry
13
that is
10
utilized for the entire memory block
10
. That is, a common decode circuitry
12
and I/O circuitry
13
is typically utilized for the large memory block
10
.
In integrated circuit designs of the prior art, a large rectangular block of memory, such as memory block
10
,
20
, or
30
of
FIG. 1
, typically comprises approximately 10 to 50 percent of the total memory implemented within the integrated circuit. Therefore, each block of memory typically provides a relatively large percentage of the total memory implemented in an integrated circuit. Also, because of the relatively large size and inflexible shape of prior art memory blocks, a relatively small number of blocks are typically implemented within an integrated circuit
100
of the prior art. For example, in prior art designs, typically no more than 10 memory blocks are implemented within an integrated circuit. Moreover, the memory blocks implemented in integrated circuits that comprise non-memory components are typically larger in size than most of the non-memory components implemented within such integrated circuit. For example, in a microprocessor chip
100
, memory blocks
10
,
20
, and
30
are typically larger than most of the non-memory components contained within the CPU core
40
, such as the ALU, floating point execution unit, etcetera.
Because the memory blocks
10
,
20
, and
30
of the prior art are typically implemented only as relatively large, rectangular blocks of memory, the organization of such memory within the chip
100
is very inflexible. For example, suppose in developing the core
40
for chip
100
a component, shown as component
42
, needs to expand in size, thus requiring such component
42
to consume more surface space. For example, suppose that in designing component
42
, it had to expand in size, in the manner illustrated in
FIG. 1
, in order to achieve its performance target. As shown in
FIG. 1
, it may be necessary for component
42
to expand such that it violates the boundary of rectangular cache block
10
. Such a violation of cache block
10
is extremely problematic in prior art designs because it is very difficult to redesign prior art cache block
10
around the expanding component
42
. For example, it is very difficult to redesign cache block
10
such that its upper, lefthand corner is cut out to make room for the expanding component
42
. Therefore, such a redesign of cache block
10
would typically be very complex and time consuming, and therefore presents a large cost obstacle in designing the cache block
10
around the changing composition of the chip, as needed. For example, the large arrays of the prior art depend on their rectangular structure to share drivers and decoders.
Because of the great difficulty involved in redesigning such prior art cache block
10
to various shapes and sizes to respond to the changing composition of a chip (e.g., the expansion of component
42
), designers typically respond to such changes in composition by moving (or relocating) an entire memory block within the chip. So, for example, in response to the changing size of component
42
, which would otherwise violate the boundary of cache block
10
, a designer of the prior art chip
100
would typically attempt to relocate the entire cache block
10
to a new location on chip
100
. Often, such a relocation of the large, rectangular cache block
10
results in an undesirably large amount of white space (i.e., unused surface space of a chip) on the die. Additionally, sufficiently large blocks of space may not be available on the surface of chip
100
in which to relocate such a large rectangular block of cache. Thus, a smaller overall amount of cache memory may have to be implemented within chip
100
because sufficient large blocks of space are not available for implementing one or more of the large rectangular blocks
10
,
20
, and
30
. For example, because the memory block
10
is likely much larger than the non-memory component
42
, it is difficult to rearrange the memory block
10
around the expanding non-memory component
42
in a desirable manner (e.g., that does not result in a large amount of white space on the chip
100
.) Therefore, organizing memory blocks within a chip of the prior art is typically a very difficult and complex task because of the inflexibility of the large, rectangular blocks commonly implemented in such prior art designs. That is, the large, rectangular blocks of memory typically implemented in prior art designs are very inflexible and result in great difficulty in reorganizing such memory blocks in response to changes in the composition of a chip.
In memory architecture of the prior art, memory blocks, such as blocks
10
,
20
, and
30
of
FIG. 1
, are commonly im

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