Flexible architecture for an embedded interrupt controller

Details Flexible architecture for an embedded interrupt controller Flexible architecture for an embedded interrupt controller

2000-05-05

2002-06-04

Dharia, Rupal (Department: 2181)

Electrical computers and digital data processing systems: input/

Interrupt processing

C710S266000, C710S300000

Reexamination Certificate

active

06401154

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This application relates to microcontroller architecture, and more particularly to a programmable interrupt controller.
2. Description of the Related Art
A typical interrupt controller has 8 input lines that take requests from one of 8 different devices. The controller then passes the request on to the processor, telling it which device issued the request (which interrupt number triggered the request, from 0 to 7). The original PC and XT systems had one of these controllers, and hence supported interrupts 0 to 7 only.
Starting with the IBM AT, a second interrupt controller was added to the system to expand it; this was part of the expansion of the ISA system bus from 8 to 16 bits. In order to ensure compatibility, the designers of the AT didn't want to change the single interrupt line going to the processor. So what they did instead was to cascade the two interrupt controllers together.
The first interrupt controller still has 8 inputs and a single output going to the processor. The second one has the same design, but it takes 8 new inputs (doubling the number of interrupts) and output its single feed into input line
2
of the first controller. If any of the inputs on the second controller become active, the output from that controller triggers interrupt #
2
on the first controller, which then signals the processor.
SUMMARY OF THE INVENTION
Briefly, the illustrative system provides an interrupt controller with the flexibility to provide a PC/AT-compatible or non-PC/AT-compatible embedded environment. Multiple slave controllers together with a master controller are combined with a multi-channel routing switch matrix. Flexibility is provided through interrupt sharing and selective slave controller disabling. The switch matrix, under software control, directs the multiple interrupt signals from internal and external sources to any priority channel of the multi-stage interrupt controller. Configuration of the switch matrix may be performed upon initialization or during run time. The switch matrix, slave controllers and master controller cascade formation may be configured to utilize a large number of interrupt channels or alternatively, to operate under PC/AT compatibility using a reduced number of interrupt channels.


REFERENCES:
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patent: 6163826 (2000-12-01), Khan et al.
Elan™SC400 and ElanSC410 Microcontrollers User'Manual, Advanced Micro Devices, Inc., ©1997, pp. 10-1 through 10-10.
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82C54 CHMOS Programmable Interval Timer, Intel Corporation, Sep. 1993, pp. 5-24 through 5-29.
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Elan™ SC400 and Elan SC410 Single-Chip, Low-Power, PC/AT-Compatible Microcontrollers, Data Sheet, Advanced Micro Devices, Inc., Dec. 1998, pp. 1 through 132.
Elan™ SC410 Microcontroller, Product Brief, Advanced Micro Devices, Inc., ©1999, 3 pages, http://www.amd.com/products/lpd/elan410/21328a.html.

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