Flexible and efficient configuration of multiple common...

Details Flexible and efficient configuration of multiple common... Flexible and efficient configuration of multiple common...

2008-06-04

2011-11-08

Tsai, Henry (Department: 2184)

Electrical computers and digital data processing systems: input/

Input/output data processing

Data transfer specifying

C709S220000

Reexamination Certificate

active

08055813

ABSTRACT:
In a system for communicating data from a processor to a plurality of register groupings that includes a plurality of registers and a plurality of register decoding logic entities, each register is associated with one of the plurality of register groupings. The plurality of register decoding logic entities is arranged in a data communication ring and is assigned to a register grouping. Each register decoding logic entity is configured to: receive a data packet that includes a data unit intended for a set of the registers in communication with the register decoding logic entity; write the data unit to each of the set of registers; determine if the register decoding logic entity is set to a relay mode; and if the register decoding logic entity is set to the relay mode, then update the data packet to reflect an address corresponding to a next register decoding logic entity in the data communication ring and then transmit the data packet to the next register decoding logic entity for which the data packet is intended.

REFERENCES:
patent: 5867501 (1999-02-01), Horst et al.
patent: 5872783 (1999-02-01), Chin
patent: 7174371 (2007-02-01), Elo et al.
patent: 2002/0110086 (2002-08-01), Reches

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