Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area
Reexamination Certificate
2001-10-23
2004-04-13
Elmore, Reba I. (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Shared memory area
C711S006000, C711S153000, C711S203000
Reexamination Certificate
active
06721857
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to storage and computing systems, and more particularly to flexible storage and computing systems.
BACKGROUND OF THE INVENTION
When designing and building complex electronic systems such as storage arrays or computer systems, the designer typically begins with the architecture. The architecture of the system defines the function of each component and the communication paths between the components. Referring now to
FIG. 1
, a conventional storage architecture
10
that provides 2×360 Mb/s is illustrated and typically includes one or more disk controllers
12
-
1
,
12
-
2
. . . ,
12
-
n
that control and are directly connected to one or more disk drives
14
-
1
,
14
-
2
, . . . ,
14
-
n
. The disk controllers
12
are directly connected to one or more data buses
18
-
1
,
18
-
2
, . . .
18
-
n
. Channel cards/processors
20
-
1
,
20
-
2
,
20
-
3
, . . . and
20
-
n
are also connected to the data buses
18
.
The disk drives
14
employ internal rotating magnetic storage or other electronic storage media to save/retrieve data. The disk controllers
12
fulfill read/write requests to/from cache memory (not shown). One or more host computer systems are connected to the storage architecture
10
using one or more host interface processors
24
-
1
,
24
-
2
,
24
-
3
. . . and
24
-
n.
While the storage architecture
10
works well when the functional requirements of the storage architecture
10
remain relatively static, the storage architecture
10
is not capable of handling functional changes without a redesign. In other words, the storage architecture is relatively fixed, inflexible, and capable of only very limited expansion. The data busses have pre-defined (hardware limited) throughput, expandability and component connectability. The individual components of the storage architecture
10
such as the channel processors
20
, cache memory, disk controllers
12
and disk drives
14
also contain internal processing, storage and communication limitations that must be accommodated.
All of the components of the storage architecture
10
have very constrained functionality. The components limit the types of devices that may request service and the resources that are available to provide the requested service. For example, the disk controller
12
receives requests via a narrowly defined application protocol interface (API) to save/retrieve data. The disk controller
12
services the requests via disk drives
14
that are hardwired to the disk controller
12
. The disk drives
14
can only respond to a predefined program interface such as small computer system interface (SCSI).
Due to the need for instant capacity on demand (ICOD) in the computer storage industry, hot spare disks at a customer's site are usually required. Hot spare disks can account for 25% of a $2,000,000 disk array. In other words, approximately $500,000 of the disk array is idle and not returning value to the owner. Some data centers have ten $2,000,000 disk arrays. These data centers typically have approximately $5,000,000 in unused disk array equipment at a given time. The unused disk array equipment occupies raised floor space, consumes power, and generates heat. In addition, the unused disk array equipment provides no return on assets (ROA) value other than insurance against future storage needs.
SUMMARY OF THE INVENTION
A virtual storage and computing device according to the present invention includes an array control processor that includes a transceiver and that stores a virtual device blueprint. Shared memory is linked to the array control processor. The array control processor uses a wireless link to request additional resources from at least one component selected from the group of disk controllers, disk drives, cache memory, shared memory and channel adapters to assemble a virtual device described by the virtual device blueprint.
According to other features of the invention, the shared memory and cache memory are hardwired and/or wireless links to the array control processor. The virtual device blueprint defines a disk array. The array control processor includes firmware that stores the virtual device blueprint.
According to still other features of the invention, the array control processor receives the virtual device blueprint from a host computer that is linked to the array control processor using a channel adapter. Alternately, the array control processor receives the virtual device blueprint via a wireless link between a host computer and the array control processor.
In still other features, the array control processor transmits a request for a disk controller having first specifications. First and second disk controllers respond to the request and meet the first specifications. The array control processor selects one of the first and second disk controllers based on transmission power requirements of the first and second disk controllers.
In yet other features, the array control processor transmits a first request for a disk controller having first specifications. A third disk controller responds to the request by indicating availability of the third disk controller and by indicating that the third disk controller does not yet meet the first specifications. The third disk controller transmits a second request for available disk drives to obtain the requested specifications.
Further areas of applicability of the present invention will become apparent from the detailed description provided hereinafter. It should be understood that the detailed description and specific examples, while indicating the preferred embodiment of the invention, are intended for purposes of illustration only and are not intended to limit the scope of the invention.
REFERENCES:
patent: 5367637 (1994-11-01), Wei
patent: 6578129 (2003-06-01), da Silva Junior et al.
Cochran Robert A.
Robinson David A.
Elmore Reba I.
Hewlett--Packard Development Company, L.P.
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