Static information storage and retrieval – Read/write circuit – Bad bit
Patent
1993-09-27
1996-02-13
Nelms, David C.
Static information storage and retrieval
Read/write circuit
Bad bit
36523003, 371 102, 371 103, G11C 700, G11C 2900
Patent
active
054916640
ABSTRACT:
An apparatus and method for implementing flexible redundancy memory block elements in a divided array architecture scheme. The apparatus comprising the plurality of memory sub-arrays. Each of the memory sub-arrays includes a plurality of memory blocks having unique addresses and at least one redundancy memory block having a programmable element. Each of the memory sub-arrays is coupled to a plurality of global wordlines which are not uniquely addressed. The memory sub-arrays, namely the memory and redundancy memory blocks, are coupled to a true global read bus to allow the redundancy memory in one memory sub-array to be shared by another sub-array. The method comprises the steps needed to practice the present invention.
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Cypress Semiconductor Corporation
Mai Son
Nelms David C.
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