Etching a substrate: processes – Masking of a substrate using material resistant to an etchant – Resist material applied in particulate form or spray
Reexamination Certificate
2000-06-02
2002-04-30
Gulakowski, Randy (Department: 1746)
Etching a substrate: processes
Masking of a substrate using material resistant to an etchant
Resist material applied in particulate form or spray
C216S011000, C216S017000, C216S047000, C216S024000, C445S024000, C445S050000
Reexamination Certificate
active
06379572
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to flat panel displays and more particularly to flat panel displays with spaced apart gate holes.
BACKGROUND ART
The cathode-ray tube (CRT) displays have been the predominant display technology for purposes such as home television and computer systems. For many applications, CRTs have advantages in terms of superior color resolution, high contrast and brightness, wide viewing angles, fast response times, and low manufacturing costs. However, CRTs also have major drawbacks such as excessive bulk and weight, fragility, high power and voltage requirements, strong electromagnetic emissions, the need for implosion and x-ray protection, undesirable analog device characteristics, and a requirement for an unsupported vacuum envelope that limits screen size.
To address the inherent drawbacks of CRTs, alternative display technologies have been developed. These technologies generally provide flat panel displays, and include liquid crystal displays (LCDs), both passive and active matrix, electroluminescent displays (ELDs), plasma display panels (PDPs), vacuum fluorescent displays (VFDs) and field emission displays (FEDs).
The FED offers great promise as an alternative flat panel display technology. Its advantages include low cost of manufacturing as well as the superior optical characteristics generally associated with the CRT display technology. Like CRTs, FEDs are phosphor based and rely on cathodoluminescence as a principle of operation. FEDs rely on electric field or voltage induced emissions to excite the phosphors by electron bombardment rather than the temperature induced emissions used in CRTs. To produce these emissions, FEDs have generally used row-and-column addressable cold cathode emitters of which there are a variety of designs, such as point emitters (also called cone, microtip, or “Spindt” emitters), wedge emitters, thin film amorphic diamond emitters, and thin film edge emitters.
Each of the FED emitters is typically a miniature electron gun of micron dimensions. A row electrode deposited on a baseplate acts as a cathode and a transparent electrode on a transparent faceplate acts as an anode. An insulator and a resistor separate the row electrode from a column electrode and the column electrode is connected to a gate electrode.
A “gate hole” is formed in the gate electrode and an emitter cavity is formed through the gate hole into the insulator down to the resistor. The gate hole is used as the pattern to deposit the emitter in the emitter cavity so that the tip of the emitter is adjacent the gate electrode.
When a sufficient voltage is applied between the emitter, coupled by the resistor to the row electrode, and an adjacent gate electrode, electrons are emitted from the emitter into a vacuum, which is located between a baseplate, upon which the emitters are mounted, and a faceplate having a transparent anode surface to which the phosphors are applied. The emitted electrons are attracted and accelerated to strike the phosphors on the faceplate. The phosphors then emit visible light which form picture elements, or pixels, which make up the images on the face of the FED.
One of the major problems with the FED is in the manufacture of the gate and the gate holes. As the size of the FED panels increase in size, it is necessary to decrease the diameters of the gate holes in order to reduce the driving voltage for the emitters which are driven by charges on the gate. To do this, various techniques have been developed including one of using microspheres as masks for the etching of the gate holes.
The microspheres are deposited on the gate, an etch resistant material is deposited on the microspheres and the gate, the microspheres with the etch resistant material are removed leaving the negative pattern of the etch resistant material on the gate, and the gate holes are etched in the gate where it is free from the etch resistant material.
The difficulty with this technique is that the microspheres randomly stick together and form sets of gate holes which run into each other, referred to a “doublets”, and which prevent the proper formation of the emitters.
This is a major problem facing FEDs manufactured by this process, but no satisfactory solution has heretofore been discovered.
DISCLOSURE OF THE INVENTION
The present invention provides a method for manufacturing a flat panel in which a soft mask material is deposited over the flat panel. Microspheres are deposited on the soft mask material and an isotropic etch uses the microspheres as a mask to etch the soft mask material to form soft mask portions under the microspheres. The microspheres are removed and a hard mask material is deposited over the soft mask portions. The hard mask material is processed and chemical mechanical polished down to the soft mask portions which are removed by etching to leave a hard mask which is used in an ansotropic etching process to form holes in the flat panel. The holes are spaced apart with no doubling and smaller holes are possible than with the prior art.
The present invention provides a method for manufacturing a flat panel display in which a baseplate has a conductive row electrode deposited on it followed by an insulator. A conductive gate electrode is deposited over the insulator and a soft mask material is deposited over the conductive gate electrode. Microspheres are deposited on the soft mask material and an isotropic etch uses the microspheres as a mask to etch the soft mask material to form soft mask portions under the microspheres. The microspheres are removed and a hard mask material is deposited over the soft mask portions. The hard mask material is processed and chemical mechanical polished down to the soft mask portions which are removed by etching to leave a hard mask which is used by anisotropic etch process to form gate holes in the gate electrode. The gate holes are used to form emitter cavities into which emitters are deposited. The gate holes are spaced apart with no doubling and smaller gate holes are possible than with the prior art.
The above and additional advantages of the present invention will become apparent to those skilled in the art from a reading of the following detailed description when taken in conjunction with the accompanying drawings.
REFERENCES:
patent: 5669800 (1997-09-01), Ida et al.
patent: 5700627 (1997-12-01), Ida et al.
patent: 5817373 (1998-10-01), Cathy et al.
patent: 5865659 (1999-02-01), Ludwig et al.
patent: 6080325 (2000-06-01), Cathy et al.
patent: 6083767 (2000-07-01), Tjaden et al.
M. Ida, B. Montmayeul, and R. Meyer, “New Microlithography Technique for Large Size Field Emission Displays”, LETI-CEA, Grenoble, France, Oct. 1996.
Kikuchi Kazuo
Kubota Shinji
Ahmed Shamin
Gulakowski Randy
Ishimaru Mikio
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