Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-04-12
2003-11-11
Tran, Thien (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S348000, C257S349000, C257S350000
Reexamination Certificate
active
06646308
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a flat panel display device and a method of a manufacturing the same, and, more particularly, to a flat panel display device with improved electrical characteristics and reduced current leakage.
2. Description of Related Art
FIG. 1
is a cross-sectional view illustrating a conventional organic EL display device. A method of manufacturing the conventional organic EL display device is described below with reference to FIG.
1
.
A buffer layer
12
is formed on a transparent substrate
11
. The transparent substrate
11
is made of a glass or a synthetic resin. A poly silicon layer is deposited on the buffer layer
12
and patterned into a semiconductor layer
20
using a first mask. A first insulating layer
25
is formed over the entire surface of the transparent substrate
11
.
Then, a first metal layer is deposited on the first insulating layer
25
and patterned into a gate electrode
35
using a second mask. Using the gate electrode
35
as a mask, an n-type impurity or a p-type impurity is ion-implanted into the semiconductor layer
20
to form source and drain regions
26
and
27
.
Thereafter, a second insulating layer
30
is formed over the entire surface of the transparent substrate
11
. The second insulating layer
30
serves as an interlayer insulating layer. Using a third mask, contact holes
31
and
32
are formed in the interlayer insulating layer
30
. The contact holes
31
and
32
expose portions of the source and drain regions
26
and
27
, respectively.
A second metal layer is deposited on the second insulating layer
30
, filling into the contact holes
31
and
32
. The second metal layer is patterned using a fourth mask to form source and drain electrodes
50
and
55
. The source and drain electrodes
50
and
55
are electrically connected to the source and drain regions
26
and
27
through the contact holes
31
and
32
, respectively.
Subsequently, a third insulating layer
40
is formed over the entire surface of the transparent substrate
11
. Using a fifth mask, the third insulating layer
40
is etched to form a via hole
41
at a location corresponding to either of the source and drain electrodes
50
and
55
. In
FIG. 1
, the via hole
41
is formed at a location corresponding to a portion of the drain electrode
55
.
A transparent conductive material layer is deposited on the third insulating layer
40
and patterned using a sixth mask to form a pixel electrode
60
. The pixel electrode
60
serves as an anode electrode. The pixel electrode
60
is electrically connected to either of the source and drain electrodes
50
and
55
through the via hole
41
. In
FIG. 1
, the pixel electrode
40
is electrically connected to the drain electrode
55
through the via hole
41
.
A fourth insulating layer
70
is formed over the entire surface of the transparent substrate
11
. The fourth insulating layer
70
serves as a planarization layer. The fourth insulating layer
70
is etched using a seventh mask to form an opening portion
71
. The opening portion
71
exposes a portion of the pixel electrode
60
. An organic EL layer
80
is formed on the exposed portion of the pixel electrode
60
to cover the opening portion
71
. Then, a cathode electrode
90
is formed to cover the organic EL layer
80
. Therefore, the conventional organic EL display device is completed.
As described above, the method of manufacturing the conventional organic EL display device requires a seven-mask process. Therefore, this presents the difficulty that the manufacturing process is complicated and the production cost is increased.
Also, since the gate electrode
35
is used as a mask during an ion-implanting process to form the source and drain regions
26
and
27
, the gate electrode
35
may become damaged during manufacturing, thereby deteriorating electrical characteristics of the flat panel display device.
In addition, when a lightly doped drain (LDD) structure or an offset structure is employed in order to improve an on/off current ratio, an additional mask process is required. In that case, a process to anodize the gate electrode can be employed so that an additional mask process is not required. However, this requires additional equipment for the anodizing process, thereby increasing the production cost.
SUMMARY OF THE INVENTION
To overcome the difficulties described above, preferred embodiments of the present invention provide a flat panel display device having a simplified manufacturing process.
It is another object of the present invention to provide a flat panel display device having excellent electrical characteristics.
It is a still object of the present invention to provide a flat panel display device which can reduce a leakage current.
In order to achieve the above objects, the preferred embodiments of the present invention provide a flat panel display device, comprising: a semiconductor layer formed on an insulating substrate; source and drain electrodes directly contacting both end portions of the semiconductor layer, respectively; a pixel electrode having an opening portion formed thereon; a first insulating layer formed over the remaining portion of the insulating substrate except for the opening portion; a gate electrode formed on a portion of the first insulating layer over the semiconductor layer; and source and drain regions formed in both end portions of the semiconductor layer.
The source and drain electrodes include a pixel electrode material layer, a metal material layer and a capping insulating material layer stacked sequentially. The pixel electrode extends from either of the source and drain electrodes. The organic EL display device further includes a storage capacitor including first and second capacitor electrodes with a dielectric layer interposed therebetween. The first capacitor electrode includes the pixel electrode material layer and the metal material layer stacked sequentially. The second capacitor electrode includes a gate electrode material layer. The dielectric layer includes the capping insulating layer and the first insulating layer stacked sequentially.
The source and drain regions include an offset region formed in a portion of the semiconductor layer between the source and drain electrodes and the gate electrode. The source and drain regions include low-density source and drain regions formed in a portion of the semiconductor layer between the source and drain electrodes and the gate electrode, thereby forming a lightly doped drain (LDD) structure.
The organic EL display device further includes first and second spacers. The first spacer is formed on side wall portions of the source and drain regions. The second spacer is formed on side wall portions of the gate electrode and the opening portion. The organic EL display device further includes a second insulating layer for planarization on the remaining portion of the first insulating layer except for the opening portion. The gate electrode includes a metal material layer and a capping insulating layer stacked sequentially.
The present invention further provides a method of manufacturing a flat panel display device, comprising: forming a semiconductor layer on an insulating layer; ion-implanting an impurity having a first conductivity into the semiconductor layer; forming source and drain electrodes, the source and drain electrodes directly contacting both end portions of the semiconductor layer; ion-implanting an impurity having a second conductivity into the semiconductor layer to form high-density source and drain regions and a channel area, the high-density source and drain regions directly contacting the source and drain electrodes; forming a first insulating layer over the entire surface of the insulating substrate; forming a pixel electrode having an opening portion formed thereon; and forming a gate electrode on a portion of the first insulating layer over the semiconductor layer.
The method further includes forming a contact hole contemporaneously with forming the pixel elec
Park Sang-Il
So Woo-Young
Yoo Kyung-Jin
McGuireWoods LLP
Samsung SDI & Co., Ltd.
Tran Thien
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