Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing
Reexamination Certificate
2005-04-05
2005-04-05
Bataille, Pierre-Michel (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Access timing
C711S103000, C711S169000, C365S189050
Reexamination Certificate
active
06877080
ABSTRACT:
A synchronous flash memory includes an array of non-volatile memory cells. The memory device has a package configuration that is compatible with an SDRAM. The memory device includes a pipelined buffer with selectable propagation paths to route data from the input connection to the output connection. Each propagation path requires a predetermined number of clock cycles. The non-volatile synchronous memory includes circuitry to route both memory data and register data through the pipelined output buffer to maintain consistent latency for both types of data.
REFERENCES:
patent: 5041886 (1991-08-01), Lee
patent: 5537354 (1996-07-01), Mochizuki
patent: 5541886 (1996-07-01), Hasbun
patent: 5579267 (1996-11-01), Koshikawa
patent: 5600605 (1997-02-01), Schaefer
patent: 5666321 (1997-09-01), Schaefer
patent: 5751039 (1998-05-01), Kauffman
patent: 5765010 (1998-06-01), Chung et al.
patent: 5787457 (1998-07-01), Miller
patent: 5801985 (1998-09-01), Roohparvar
patent: 5808946 (1998-09-01), Roohparvar
patent: 5835956 (1998-11-01), Park
patent: 5890193 (1999-03-01), Chevallier
patent: 5917761 (1999-06-01), Tietjen
patent: 5936903 (1999-08-01), Jeng
patent: 5978311 (1999-11-01), Wilford
patent: 5995438 (1999-11-01), Jeng
patent: 6026465 (2000-02-01), Mills
patent: 6044023 (2000-03-01), Proebsting
patent: 6081477 (2000-06-01), Li
patent: 6085282 (2000-07-01), Hansen
patent: 6137133 (2000-10-01), Kauffman
patent: 6141247 (2000-10-01), Roohparvar
patent: 6154418 (2000-11-01), Li
patent: 6154821 (2000-11-01), Barth
patent: 6173345 (2001-01-01), Stevens
patent: 6301269 (2001-10-01), Tayloe et al.
patent: 6472922 (2002-10-01), Paluch, Jr.
patent: 0 978 842 (2000-09-01), None
patent: WO 200175896 (2001-10-01), None
“Self-Timed Hit Circuit for a Content Addressable Memory”, IBM Technical Disclosure Bulletin, vol. 38, No. 2, Feb. 1, 1995, pp. 65-66.*
Keeth, et al., “DRAM circuit design: a tutorial,” IEEE Press, 2001, pp. 16-23, 142-153.
Micron Semiconductor Products, Inc., “2Mb, Smart 5 BIOS-Optimized Boot Block Flash Memory,”Flash Memorywww.micron.com, copyright 2000, Micron Technology, Inc., pp. 1-12.
Micron, “16 Mb: x16 SDRAM”Synchronous DRAM, www.micron.com, copyright 1999 Micron Technology, Inc., pp. 1-51.
Bataille Pierre-Michel
Leffert Jay & Polglaze PA
Micro)n Technology, Inc.
LandOfFree
Flash with consistent latency for read operations does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Flash with consistent latency for read operations, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Flash with consistent latency for read operations will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3373761