Flash with consistent latency for read operations

Details Flash with consistent latency for read operations Flash with consistent latency for read operations

2000-05-10

2003-09-02

Bataille, Pierre M. (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

C711S167000, C365S189050

Reexamination Certificate

active

06615307

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
The present invention relates generally to non-volatile memory devices and in particular the present invention relates to a synchronous non-volatile flash memory.
BACKGROUND OF THE INVENTION
Memory devices are typically provided as internal storage areas in the computer. The term memory identifies data storage that comes in the form of integrated circuit chips. There are several different types of memory. One type is RAM (random-access memory). This is typically used as main memory in a computer environment. RAM refers to read and write memory; that is, you can both write data into RAM and read data from RAM. This is in contrast to ROM, which permits you only to read data. Most RAM is volatile, which means that it requires a steady flow of electricity to maintain its contents. As soon as the power is turned off, whatever data was in RAM is lost.
Computers almost always contain a small amount of read-only memory (ROM) that holds instructions for starting up the computer. Unlike RAM, ROM cannot be written to. An EEPROM (electrically erasable programmable read-only memory) is a special type non-volatile ROM that can be erased by exposing it to an electrical charge. Like other types of ROM, EEPROM is traditionally not as fast as RAM. EEPROM comprise a large number of memory cells having electrically isolated gates (floating gates). Data is stored in the memory cells in the form of charge on the floating gates. Charge is transported to or removed from the floating gates by programming and erase operations, respectively.
Yet another type of non-volatile memory is a Flash memory. A Flash memory is a type of EEPROM that can be erased and reprogrammed in blocks instead of one byte at a time. Many modern PCS have their BIOS stored on a flash memory chip so that it can easily be updated if necessary. Such a BIOS is sometimes called a flash BIOS. Flash memory is also popular in modems because it enables the modem manufacturer to support new protocols as they become standardized.
A typical Flash memory comprises a memory array that includes a large number of memory cells arranged in row and column fashion. Each of the memory cells includes a floating gate field-effect transistor capable of holding a charge. The cells are usually grouped into blocks. Each of the cells within a block can be electrically programmed in a random basis by charging the floating gate. The charge can be removed from the floating gate by a block erase operation. The data in a cell is determined by the presence or absence of the charge in the floating gate.
A synchronous DRAM (SDRAM) is a type of DRAM that can run at much higher clock speeds than conventional DRAM memory. SDRAM synchronizes itself with a CPU's bus and is capable of running at 100 MHZ, about three times faster than conventional FPM (Fast Page Mode) RAM, and about twice as fast EDO (Extended Data Output) DRAM and BEDO (Burst Extended Data Output) DRAM. SDRAM's can be accessed quickly, but are volatile. Many computer systems are designed to operate using SDRAM, but would benefit from non-volatile memory.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a non-volatile memory device that can operate in a manner similar to SDRAM operation.
SUMMARY OF THE INVENTION
The above-mentioned problems with memory devices and other problems are addressed by the present invention and will be understood by reading and studying the following specification.
In one embodiment, the present invention provides a non-volatile synchronous flash memory that is compatible with existing SDRAM package pin assignments. It will be apparent from reading the detailed description that system designers with knowledge in SDRAM applications could easily implement the present invention to improve system operation.
In one embodiment, a synchronous memory device comprises a pipeline buffer having an input connection and an output connection. The pipeline buffer has a plurality of selectable propagation paths to route data from the input connection to the output connection wherein each propagation path requires a predetermined number of clock cycles. The memory includes a multiplex circuit coupled to the input of the pipeline buffer. The multiplex circuit has a first and second input. A data register circuit is coupled to the first input of the multiplex circuit, and a data read circuit is coupled to the second input of the multiplex circuit. The data read circuit provides output data read from a memory array of the synchronous memory device.
In another embodiment, a processing system comprises a memory controller, and a synchronous flash memory device coupled to the memory controller. The memory controller receives memory cell data from the synchronous flash memory device a first predetermined number of clock cycles after a memory column address has been provided by the memory controller. The memory controller also receives status data from the synchronous flash memory device a second predetermined number of clock cycles after a status read request has been provided by the memory controller. The first and second predetermined number of clock cycles are equal.
A method of reading from a synchronous flash memory device is provided. The method comprises initiating a memory cell read operation, and outputting memory cell data in response to the memory cell read operation. The memory cell data is output on data connections a predetermined number of clock cycles after the memory cell read operation is initiated. The method includes initiating a status read operation, and outputting status data in response to the status read operation. The status data is output on the data connections the predetermined number of clock cycles after the status read operation is initiated.


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