Static information storage and retrieval – Read/write circuit – Erase
Patent
1993-04-21
1993-12-28
Fears, Terrell W.
Static information storage and retrieval
Read/write circuit
Erase
G11C 1300
Patent
active
052745996
ABSTRACT:
A flash-type nonvolatile semiconductor memory having a precise erasing level is disclosed. The memory of the present invention includes a plurality of source lines arranged in parallel to bit lines in correspondence with columns of a cell matrix, a plurality of level judging circuits arranged at each bit line and a plurality of source line switches arranged at each source line. In an erasing operation, memory cells are erased so as to not generate over-erased cells, every selected memory cell is simultaneously tested whether or not it has a threshold less than a upper limit of an object range, and only unsufficiently erased memory cells are further erased in a re-erasing step by being controlled with the source line switches.
REFERENCES:
patent: 5065364 (1991-11-01), Atwood et al.
Fears Terrell W.
Fujitsu Limited
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