Flash memory with trench select gate and fabrication process

Details Flash memory with trench select gate and fabrication process Flash memory with trench select gate and fabrication process

2005-05-17

2005-05-17

Wilson, Christian (Department: 2824)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S315000, C257S316000

Reexamination Certificate

active

06894339

ABSTRACT:
Flash memory and process of fabrication in which memory cells are formed with select gates in trenches between stacked, self-aligned floating and control gates, with buried source and drain regions which are gated by the select gates. Erase paths are formed between projecting rounded edges of the floating gates and the select gates, and programming paths extend from the mid-channel regions between the select gates and floating gates through the gate oxide to the edges of the floating gates. Trenched select gates can be provided on one or both sides of the floating and control gates, depending upon array architecture, and the stacked gates and dielectric covering them are used as a self-aligned mask in etching the substrate and other materials to form the trenches.

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