Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Reexamination Certificate
1999-07-01
2003-12-30
Kim, Matthew (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
C711S167000, C713S002000, C713S300000, C365S185330, C365S185230, C365S185250
Reexamination Certificate
active
06671769
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention relates generally to memory devices and in particular the present invention relates to fast access of a boot block in a flash memory device.
BACKGROUND OF THE INVENTION
Typical flash memories comprise a memory array having a large number of memory cells arranged in blocks. Each of the memory cells is fabricated as a field-effect transistor having a control gate and a floating gate. The floating gate is capable of holding a charge, and is separated, by a layer of thin oxide, from source and drain regions contained in a substrate. Each of the memory cells can be electrically programmed (charged) by injecting electrons from the drain region through the oxide layer onto the floating gate. The charge can be removed from the floating gate by tunneling the electrons to the source through the oxide layer during an erase operation. Thus, the data in a memory cell is determined by the presence or absence of a charge on the floating gate.
To read the memory cells, a voltage is applied to the gate of the memory cells. By changing the threshold voltage of the memory cell transistor, the level of activation of the transistor can be measured using sense amplifier circuitry. Flash memories have a typical word line voltage which is coupled to the memory cell transistor of about 5 volts during a read operation. In low voltage memory devices, a charge pump may be needed to raise a supply voltage to an acceptable word line voltage. For example, a charge pump is needed to raise a 3 volt power supply to a word line voltage of 5 volts.
The array of the flash memory devices typically is divided into multiple addressable blocks of memory cells. Each block of memory cells can store data used during system operations. For example, when the flash memory is used in a processing, or computer system, the memory can be used to store system boot instructions. The process of booting a processor comprises loading the first piece of software that starts the processor. Because an operating system is essential for running programs, it is usually the first piece of software loaded during the boot process.
System operation requires fast access to the boot data during power-up to maintain acceptable performance for the processing system. Currently, the entire flash memory array is provided with a word line voltage on power-up that is sufficient to read any memory cell in the flash memory for retrieving the boot data. This can create problems with low voltage memory devices.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for allowing fast reading of system boot information without requiring a large voltage pump circuit.
SUMMARY OF THE INVENTION
In one embodiment, a method of operating a flash memory, the method comprises activating the flash memory, and providing valid processor boot data on an output data connection of the flash memory within a first time period following activation of the flash memory. The valid processor boot data is stored in an addressable boot block of memory cells of the flash memory. The method also comprises providing second valid data on the output data connection within a second time period following activation of the flash memory. The second time period is greater than the first time period, and the second valid data is stored in a second addressable block of memory cells of the flash memory.
In another embodiment, a flash memory device comprises an array of addressable memory cells arranged in addressable blocks. The addressable blocks comprise a boot block and at least one additional memory cell block. The memory device further comprises a first address decoder circuit coupled to the boot block, a first voltage pump circuit coupled to the first address decoder circuit for providing a word line voltage signal to the boot block, a second address decoder circuit coupled to the additional memory cell block, and a second voltage pump circuit coupled to the second address decoder circuit for providing a word line voltage signal to the additional memory cell block.
REFERENCES:
patent: 5339279 (1994-08-01), Toms et al.
patent: 5659501 (1997-08-01), Baldi et al.
patent: 6026465 (2000-02-01), Mills et al.
patent: 6289449 (2001-09-01), Aguilar et al.
“Flash Memory”,1998 Flash Memory Data Book,Micron Quantum Devices, Inc., p. 1-1 to p. 1-27, (1998).
Chevallier Christophe J.
Vahidimowlavi Allahyar
Anderson Matthew D.
Kim Matthew
Micro)n Technology, Inc.
Schwegman Lundberg Woessner & Kluth P.A.
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