Flash memory testing apparatus

Details Flash memory testing apparatus Flash memory testing apparatus

1994-09-12

1996-07-23

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Testing

36518533, 371 211, 371 212, G11C 2900

Patent

active

055396992

ABSTRACT:
A flash memory testing apparatus is capable of testing a flash memory while maintaining the conventional memory test functions. The flash memory testing apparatus obtains the number of programming pulses applied to each address of the flash memory. The flash memory testing apparatus executes the following steps: comparing a readout data of the flash memory under test under a writing or erasing test with an expected data output from a test pattern generator, outputting a failure signal to a failure analysis memory to store the failure data in a memory part in the failure memory in case where readout data does not coincide with an expected data, and outputting a pass signal when the readout data coincides with the expected data. The flash memory testing system has a counter for counting the number of programming pulses or erasing pulses and supplying the count data to the memory part of the failure analysis memory.

REFERENCES:
patent: 4414665 (1983-11-01), Kimura
patent: 5062109 (1991-10-01), Ohshima
patent: 5291449 (1994-03-01), Dehara
patent: 5363382 (1994-11-01), Tsukakoshi

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