Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
1999-02-04
2001-06-05
Dinh, Son T. (Department: 2824)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185300, C365S185330, C365S218000
Reexamination Certificate
active
06243299
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to memory systems and in particular to a flash memory system having a fast erase operation.
2. Background Art
Non-volatile memory systems have become increasingly popular, especially flash memory systems.
FIG. 1
shows a typical prior art flash memory cell
10
. The cell
10
is formed in a P type substrate
12
. A double diffused source region includes an inner N+ type diffusion
11
and an outer N type diffusion
15
. A single drain diffusion
16
of N+ material is formed in the substrate and spaced apart from the source diffusions
11
,
15
to form an intermediate channel region
12
a.
A floating gate
18
, typically made of doped polysilicon, is disposed over the channel region
12
a
. The floating gate 18 is electrically isolated from the other cell elements by oxide, including a thin (
100
Å) gate oxide
20
intermediate the floating gate
18
and the channel region
12
a
. A control gate
22
is disposed over the floating gate
18
and is also made of doped polysilicon. Control gate
22
is separated from the floating gate
18
by an interpoly dielectric layer
24
.
Table 1, below, shows the conventional approach to the programming, reading and erasing (two approaches) of a flash memory cell. The voltages are based upon the assumption that the primary supply voltage V
CC
for the memory is +5 volts. The conditions for programming
TABLE 1
ERASE
ERASE
PROGRAM
READ
ONE
TWO
CONTROL
+12
+5
GROUND
−10 to −17
GATE
volts
volts
volts
DRAIN
+6 to +9
+1
FLOAT
FLOAT
volts
volts
SOURCE
GROUND
GROUND
+12
+5
volts
volts
SUBSTRATE
GROUND
GROUND
GROUND
GROUND
call for the application of a high positive voltage V
G
, such as +12 volts, to the control gate
22
of the cell
10
. In addition, a moderate positive voltage V
D
of +6 to +9 volts is applied to the drain
16
and the source
11
,
15
voltage V
S
is at ground level, as is the substrate voltage V
SUB
. The current requirements for the +12 volts applied to the control gate
22
and the +6 to +9 volts applied to the drain region
16
are relatively small, this being due in part to the fact that only a few flash cells are ever programmed at one time. Thus, these voltages can be generated on the integrated circuit utilizing charge pump circuitry which is powered by the primary supply voltage V
CC
.
The above conditions result in the inducement of hot electron injection in the channel region
12
a
near the drain region
16
of the cell. These high energy electrons travel through the thin gate oxide
20
towards the positive voltage present on the control gate and collect on the floating gate
18
. These electrons will remain on the floating gate and will function to reduce the effective threshold voltage of the cell as compared to a cell which has not been programmed.
Table 1 also shows the conditions for reading cell
10
. The control gate voltage V
G
is connected to the primary supply voltage V
CC
of +5 volts. In addition, the drain voltage V
D
is set to a small positive voltage of +1 volts and the source voltage V
S
is set to ground potential. If the cell
10
were in a programmed state, the excess electrons present on the floating gate would have increased the threshold voltage to a value in excess of +5 volts. Thus, the control gate V
G
to source voltage V
S
of +5 volts would not be sufficient to turn on cell
10
. The resultant lack of cell current would indicate the programmed state of the cell. If cell
10
were in an erased state, the threshold voltage of the cell would be substantially below +5 volts. In that case, the cell
10
would conduct current which would be sensed by a sense amplifier (not depicted) thereby indicating that the cell is in the erased state.
Table 1 shows two exemplary conventional alternative sets of conditions for erasing a flash cell. In the first example, the control gate
22
voltage V
G
is grounded and the drain region
16
is left floating (open). The source region voltage V
S
is connected to a large positive voltage of +12 volts. When these conditions are applied to the cell
10
, a strong electric field is generated between the floating gate
18
and the source region
11
,
15
. This field causes the electrons on the floating gate
18
to be transferred to the source region
11
,
15
by way of Fowler-Nordheim tunneling, sometimes called cold electron injection.
The above conditions for erasing a cell have been viewed by others as disadvantageous in that the large positive voltage (+12 volts) applied to the source region is difficult to implement in an actual memory system. First, the primary supply voltage V
CC
in a typical integrated circuit memory system is +5 volts and is provided by an external power supply such as a battery. Thus, one approach would be to include a charge pump on the memory integrated circuit which is also powered by the primary supply voltage V
CC
. However, a typical integrated circuit memory system may include a million or more cells all or a very large group of which will be erased at the same time. Thus, the charge pump circuit must be capable of providing relatively large amounts of current on the order of 20 to 30 milliamperes. This has been viewed by others as impractical thus necessitating the use of an a second external supply voltage for producing the +12 volts applied to the source region. This would typically preclude battery powered operation where multiple batteries, such as a +5 volt primary supply battery and a +12 volts battery, is not practical.
The application of the relatively high voltage of +12 volts has also been viewed as disadvantageous in that there was believed to be a tendency to produce high energy holes (“hot” holes) at the surface of the source region
11
,
15
near the channel region
12
a
. These positive charges were said to have a tendency to become trapped in the thin gate oxide
20
and eventually migrate to the floating gate and slowly neutralize any negative charge placed on the floating gate during programming. Thus, over time, the programmed state of the cell may be altered. Other deleterious effects due to the presence of holes have been noted, including the undesired tendency to program non-selected cells.
The above-described disadvantages of the erase conditions set forth in Table 1 (Erase
1
) have been noted in U.S. Pat. No. 5,077,691 entitled FLASH EEPROM ARRAY WITH NEGATIVE GATE VOLTAGE ERASE OPERATION. The solution in U.S. Pat. No. 5,077,691 is summarized in Table 1 (Erase
2
). A relatively large negative voltage ranging from −10 to −17 volts is applied to the gate
22
during an erase operation. In addition, the primary supply voltage V
CC
of +5 volts (or less) is applied to the source region
11
,
15
. The drain region
16
is left floating.
Although the source current remains relatively high, the voltage applied to the source is sufficiently low that the +5 volt primary supply voltage V
CC
can be used directly or the source voltage may be derived from the primary supply voltage using a resistive divider and associated buffer. In either event, since the source voltage is equal to or less than the primary supply voltage, the large source currents required in erase operations can be provided without the use of charge pump circuitry. The high impedance control gate
22
of the flash cell draws very little current. Accordingly, the large positive voltage applied to the control gate
22
in the erase operation can be provided by a charge pump circuit. Thus, according to U.S. Pat. No. 5,077,691, only a single external power supply, the +5 volt supply for V
CC
, need be used.
In addition, the use of a relatively small source voltage equal to voltage V
CC
or less is said to decrease the magnitude of the source
11
,
15
to substrate
12
voltage. This is said to reduce the tendency for the generation of “hot” holes during erase an
Chevallier Christophe J.
Lee Roger R.
Rinerson Darrell D.
Dinh Son T.
Micro)n Technology, Inc.
Schwegman Lundberg Woessner & Kluth P.A.
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