Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Reexamination Certificate
1999-08-20
2003-07-08
Portka, Gary (Department: 2188)
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
C711S166000
Reexamination Certificate
active
06591329
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a flash memory which is a nonvolatile memory, more particularly to a flash memory system provided with a management system for appropriately managing a flash memory.
2. Discussion of the Background
As a storage medium for use in a computer system, a magnetic recording medium such as a hard disc or a floppy disc has been heretofore used. Above all, the hard disc having a large capacity and capable of operating at a high speed can store a large amount of data, and therefore it is positioned as a central storage medium of the system.
However, the manufacturing process of the hard disc is complicated, and it is difficult to realize its miniaturization, weight-saving and cost reduction. Since a structure is moved during the use of the hard disc, a relatively large consumption power is required, and particularly in the case that the hard disc is applied to a portable apparatus or the like, this problem tends to rise.
As the storage medium other than the hard disc, a flash memory is known as a nonvolatile storage element. In the flash memory, a power supply to maintain storage is unnecessary, and the miniaturization and the weight-saving are possible.
The flash memory, for structural reasons thereof, has a finite physical life of about 10
10
in terms of an rewriting times. Therefore, in order to use the flash memory relatively safely and stably for a long period of time, an expired storage element and a section in which a defect occurs are detected, and these troubles need to be avoided to store data. Furthermore, in the case of the flash memory, new data cannot be written over a section in which data has already been stored. Therefore, when the new data is to be stored, a stored area must be once erased before the data is written. However, a unit which can be erased is not an individual storage element (=bit) unit, but it is a block unit such as 4 kilobytes or 8 kilobytes. Therefore, generally, after a data portion other than the data to be rewritten is taken out of the block to be erased, the block is erased, and the data portion needs to be newly added/written again.
In Japanese Patent Application Laid-open No. 292798/1990, a flash EEprom system is described for the purpose of enhancing a writing/reading speed to a flash memory and managing a defective cell and the like. In the flash EEprom system described therein, an access time is intended to be enhanced using a cache memory. However, shortening of the access time dependent on the cache memory is naturally limited, and in order to further enhance the writing/reading speed to the flash memory, an operation speed of the entire flash memory system needs to be enhanced.
Moreover, in the above-described publication, for the management of the defective cell and the like, a redundant portion is provided with ECC and another information, and replacement bit, replacement sector and another information, and the defective cell and the like are managed only with the information of the redundant portion. However, since the defective cell and the like are managed only with the redundant portion, the storage capacity of the redundant portion has to be enlarged, which diminishes an area to store actual data. Furthermore, since the system manages the defective cell and the like only with the redundant portion, before reading the actual data, the redundant data is read, and a propriety of data stored in the memory is judged or recovery or the like of the data is performed, which remarkably delays the access time.
Additionally, the flash memory system is a nonvolatile memory, but during turning-on of a power supply or during resetting, for a controller to grasp a content and state of the flash memory, the content of the flash memory, especially the redundant data needs to be read. However, as described above, the reading speed of the flash memory is slower as compared with ordinary RAM or the like, much time is therefore required to grasp all information, and as a result, the system becomes slow in starting.
Such delay in rising is a fatal problem, for example, for a digital camera or another system which needs to be instantly ready for operation after power is turned on, and a flash memory system which can be started at a higher speed has been demanded.
SUMMARY OF THE INVENTION
An object of the present invention is to realize a flash memory system which is fast in rising speed during turning-on of a power supply or after resetting, has little delay in writing/reading time, can relatively easily perform a writing operation, can realize a high-speed operation and which can adequately manage a defective sector, defective bit or the like.
The present inventors have extended researches to enhance a writing/reading speed to the flash memory, and as a result, have proposed an address conversion table. The address conversion table formed on S-RAM or another storage medium which is accessible at a high speed correlates a logical address designated by a host computer side with an actual address of the flash memory or physical address, and mutually converts the addresses.
The address conversion table is also defined for each block as a minimum erasing unit of the flash memory, and the above-described addresses are treated as a logical block address and a physical block address, respectively. In this manner, by performing address conversion for each block corresponding to the minimum erasing unit, the management of the flash memory particularly in the writing operation is facilitated, and the writing operation can be performed at a high speed.
Moreover, an area of the logical address and an area of the physical address differ in size, and the logical address area is set smaller than the physical address area. By such setting, a difference of both areas can be used as a spare area. Specifically, the spare area is used as a queue in an operation standby state, and changed with a defective block, or used as a substitute for an area in which new data is to be written during the writing operation. This further enhances the operation speed.
Furthermore, in addition to the address conversion table, there is provided a block status table which has, as data indicating a state of each physical block on the flash memory, data indicating at least whether or not the block is good, whether or not a bad sector is present and whether or not the block is used. Since the block status table is provided, without accessing the flash memory relatively slow in the operation speed, the state of each block in the flash memory can instantly be grasped, a defective block and defective sector can easily be managed, and the operation speed is further enhanced.
Additionally, the address conversion table, block status table, queue and another internal information are usually formed on the storage medium (S-RAM) which is accessible at a high speed. However, since such storage medium is volatile, during cutting-off of power supply or during resetting, the medium is extinguished, or reliability is lost. Therefore, the storage data, i.e., the above-described internal information needs to be stored on the nonvolatile storage medium or flash memory. Then, during turning-on of the power supply or during resetting, the flash memory is accessed, and the address conversion table, block status table, queue and another internal information are restored to a previous state by the stored data.
However, the internal information changes every time the writing/reading operation to the flash memory is performed, but if every information is stored, an enormous storage area becomes necessary. Moreover, to perform such operation for each writing/reading, the longer time the storing takes, the more time is wasted, and as a result, the operation speed is decelerated. Furthermore, if during the turning-on of the power supply or during resetting all areas of the flash memory are accessed, and the address conversion table, block status table, queue and another internal information are restored, an enormous time further
Kakinuma Yuji
Kitagawa Hiroya
Shimada Teruo
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
Portka Gary
TDK Corporation
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