Flash memory system and method for controlling the same

Details Flash memory system and method for controlling the same Flash memory system and method for controlling the same

2011-03-01

2011-03-01

Chase, Shelly A (Department: 2112)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

Reexamination Certificate

active

07900118

ABSTRACT:
A flash memory system comprises a group of pages each consisting of a plurality of memory zones with various sizes; a read/write controller for controlling reading or writing of data from or to one of the pages; an error correction unit including at least two ECC (Error Correction Code) engines each encoding or decoding the data for performing error detection and correction; and an ECC judgment unit for selecting one of the ECC engines on the basis of predetermined conditions.

REFERENCES:
patent: 6769087 (2004-07-01), Moro et al.
patent: 7322002 (2008-01-01), Keays et al.
patent: 2004152194 (2004-05-01), None
patent: WO 2006-013529 (2006-02-01), None
Office Action dated Jul. 15, 2010 issued in corresponding Chinese Patent Application No. 200710096882.6.

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