Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1998-06-15
2001-06-26
Loke, Steven (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S316000, C257S317000
Reexamination Certificate
active
06252271
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a flash memory and a method of forming a flash memory, and more specifically a method of forming a flash memory cell using an asymmetric control gate with a sidewall floating gate.
2. Description of the Related Art
A flash memory is unique in providing fast compact storage which is both nonvolatile and rewritable.
In a flash memory, the threshold voltage Vt for conduction of a field effect transistor (FET) changes state depending upon the amount of charge stored in a floating gate (FG) part of the FET. The floating gate is a charge storing region which is isolated from a more traditional gate conductor CG (control gate or “wordline”) by a thin dielectric. The states of the Vt change with the amount of charge stored by the FG.
Since the FG directly controls conductivity between source and drain in a channel, the state of a FG memory cell is determined by applying certain voltages to the source or drain of the FET and observing whether the FET conducts any current.
Flash memory cells with a sidewall floating gate occupy a smaller area than those with conventional (layered) floating gates. For example, in U.S. Pat. No. 5,115,288, sidewall gates were formed on one side of the wordline by employing an extra mask. Sidewall spacers were formed on both edges of the wordline, then removed along one of the edges using the extra mask and an etching operation. Thus, the conventional approach uses a trim mask to define the floating gate.
However, this approach is expensive and requires good control of the overlay for the spacer removal mask.
Other conventional structures also are known. For example, in one structure, polysilicon spacers formed on both sidewalls are used for the floating gate. One spacer sits on top of the tunnel oxide area for programming. The other spacer is called an “added-on floating gate”. Both spacers are linked by a polysilicon body. However, a large cell size results.
In a second conventional structure, only one polysilicon spacer is used as the floating gate. A mask must be aligned to the top of the control gate, to remove the other floating gate spacer. Hence, the control gate cannot be small, since, otherwise, any misalignment will cause a problem. Therefore, this cell has difficulty in being down-scaled.
In yet another conventional structure, similar to the second conventional structure described above, a mask is needed to remove a sidewall spacer floating gate. Further, this spacer has a re-entrant corner which is very difficult to be completely removed.
Thus, the conventional methods require extra process steps, material and more precise lithographic alignment, thereby resulting in increased manufacturing costs.
SUMMARY OF THE INVENTION
In view of the foregoing and other problems of the conventional systems and methods, it is an object of the present invention to provide a method for forming a flash memory structure in which there is no (or at the very least minimal) alignment concern for high density device integration.
Another object is to provide a method for forming a flash memory which utilizes phase-shift mask techniques.
In a first aspect of the present invention, a method of forming a flash memory includes forming a polysilicon wordline with a first sidewall on a first side, the first sidewall having a predetermined slope; and forming a polysilicon spacer on a second sidewall, that is less sloped (or not sloped at all) than the first sidewall, while the polysilicon on the first sidewall is being removed (e.g., by being isotropically etched away). The step of forming the wordline includes using a phase-shift mask.
In a second aspect of the present invention, a flash memory is provided which includes a wordline (e.g., control gate) with a slope on a first side and a vertical wall on a second side prior to deposition of polysilicon spacer material. The wordline surrounds the floating gate on a plurality of sides (e.g., at least two sides), and the floating gate is self-isolated from adjacent floating gate devices by the gate conductor.
With the unique and unobvious aspects and features of the present invention, a flash memory is formed which includes a phase-shift mask, which includes less steps and material, and in which the control gate CG surrounds the floating gate (FG) on a plurality of sides (e.g., at least two sides).
Specifically, the FG is surrounded by the control gate on at least two sides. Additionally, the FG is fabricated to an extremely small size and is self-isolated from adjacent FG devices by the gate conductor.
Further, the simple process steps and self-alignment scheme of the present invention result in not only high device packing density but also decreased costs.
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Gambino Jeffrey P.
Hsu Louis L.
Mandelman Jack A.
Wheeler Donald C.
International Business Machines - Corporation
Li Todd C.
Loke Steven
McGinn & Gibb PLLC
Vu Hung Kim
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