Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-12-20
2001-07-03
Wojciechowicz, Edward (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S315000, C257S316000, C257S513000, C438S201000, C438S209000, C438S212000, C438S221000, C438S230000, C438S694000
Reexamination Certificate
active
06255689
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a flash memory structure and its method of manufacture. More particularly, the present invention relates to a vertical type of flash memory structure.
2. Description of the Related Art
Flash memory generally consists of a floating gate for storing electric charges and a control gate for controlling data transfer. The floating gate is inserted between the control gate and a substrate. The floating gate is in a ‘floating’ state because the gate is not connected any external circuits. The control gate is connected to a word line while the drain terminal of each flash memory cell is connected to a bit line.
In a conventional flash memory, neighboring flash memory cells are electrically isolated from each other by field oxide (FOX). However, field oxide tends to occupy a lot of chip area. In addition, the source/drain terminals and the floating gate of each flash memory cell also occupy a lot of chip area. If area layout of source/drain terminals and floating gates of a flash memory are reduced without changing the devices'structures, performance of the memory device will be affected.
Although shallow trench isolation can replace conventional field oxide as an electrical insulator between neighboring flash memory cells so that the level of integration is increased, area occupation of STI is still limited by photoresist resolution.
SUMMARY OF THE INVENTION
The invention provides a method of manufacturing flash memory. A substrate having a patterned mask layer thereon is provided. Using the patterned mask layer as an etching mask, the substrate is etched to form a plurality of openings in the substrate. A first liner oxide layer is formed over the exposed substrate inside the openings. Spacers are formed on the sidewalls of the openings. Each spacer has a first width at the bottom. Using the mask layer and spacers as an etching mask, the exposed substrate at the bottom of each opening is further etched to form a trench. An insulation layer is formed inside the trench, thereby forming a shallow trench isolation structure. A portion of the spacers is removed so that its first width at the bottom is reduced to a second width. The patterned mask layer is removed. A first doped region is formed in the substrate just outside the top corner region of the insulation layer, and a second doped region is formed in the substrate just underneath the former mask layer. The first doped region later functions as a source terminal while the second doped region later functions as a drain region. The spacers are removed and then a stop layer is selectively formed over the second doped regions. A tunnel oxide layer is formed on the substrate surface between the first doped region and the second doped region. Conductive spacers are next formed on the substrate sidewalls between the first doped region and the second doped region. A first dielectric layer is formed over the conductive spacers. Conductive material is deposited into the opening to form a conductive layer. The conductive layer, the first dielectric layer and the conductive spacers are subsequently patterned to form a plurality of control gates, a plurality of second dielectric layers and a plurality of floating gates.
In addition, before or after the formation of the first doped regions and the second doped regions, an additional third doped region in the substrate below the second doped region on one side of the first doped region and a fourth doped region in the substrate just under the shallow trench isolation structure may be formed. The third doped region serves as an anti-punch through implant while the fourth doped region serves as a field implant. Furthermore, polarity of the ions implanted into the substrate to form the first and the second doped region is opposite to the ions implanted into the substrate to form the third and the fourth doped region.
The invention also provides a flash memory structure. The structure includes a substrate having a protruding section and a recessed section, in which the protruding section has a sidewall and a substrate surface is located between the two sections. A tunnel oxide layer is formed on the sidewall of the protruding section and on the substrate surface between the two sections. A common drain terminal is formed at the top end of the protruding section. A source terminal is formed in the substrate region between the protruding and the recessed sections. A floating gate is formed above the tunnel oxide layer and between the source and drain terminal and a dielectric layer is formed above the floating gate. A shallow trench isolation structure is formed in the recessed section and a control gate is formed between the dielectric layer and the shallow trench isolation structure.
Accordingly, the present invention provides a method of manufacturing flash memory cells capable of increasing the level of integration. In addition, the invention also provides a method of manufacturing flash memory cells that utilizes current fabricating techniques for reducing the dimensions of isolating structures and flash memory cells. Furthermore, the invention provides a vertical type of flash memory structure capable of reducing area occupation of each flash memory cell.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 5892257 (1999-04-01), Acocella et al.
Huang Jiawei
J.C. Patents
United Microelectronics Corp.
Wojciechowicz Edward
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