Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-03-09
2001-08-28
Crane, Sara (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S315000, C257S316000, C257S317000, C257S320000, C257S321000
Reexamination Certificate
active
06281544
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a flash memory structure and its method of manufacture. More particularly, the present invention relates to a flash memory structure having a common source terminal made from a buried metal layer, whose method of manufacture is also suitable for producing a shallow trench isolation (STI) structure.
2. Description of Related Art
Conventional flash memory is a type of erasable programmable read-only memory (EPROM). There have been many articles written about flash memories. In general, the gate of a flash memory includes a polysilicon floating gate, which is used for storing electric charges, and a control gate, which is used for controlling data access. Therefore, EPROM normally has two gate terminals with the floating gate located below the control gate. The control gate and the word line are usually connected, and the floating gate is usually in a “floating” state. In other words, the floating gate is not in contact with any other circuits. An outstanding property of flash memory is its ability to perform a fast, block-by-block memory erase instead of the slow, bit-by-bit memory erase as in conventional EPROMs. Consequently, operation speed of a flash memory is very fast. Often, the entire memory can be erased within one or two seconds.
FIG. 1
is the top view of a conventional flash memory structure. In
FIG. 1
, the control gate
10
is used as a word line. The metallic bit line
12
and the control gate
10
run across each other perpendicularly. On each side of the control gate
10
, a drain region
14
and a common source
16
are present. There is a contact window
18
above the drain region
14
for coupling electrically with the bit line
12
. Furthermore, field oxide layers
13
surround the aforementioned device for insulation.
FIG. 2A
is a cross-sectional view taken along line
2
I—
2
I of
FIG. 1
that shows a conventional flash memory structure.
FIG. 2B
is a cross-sectional view taken along line
2
II—
2
II of FIG.
1
. First, as shown in
FIG. 2A
, a common source region
16
is formed within a semiconductor substrate
11
. Next, as shown in
FIG. 2B
, the common source region
16
is isolated by field oxide layers
13
, and then control gates
10
are formed above the field oxide layers
13
. The control gates
10
can be made from, for example, polysilicon. In order to avoid leakage current or other short-circuit conditions, a minimum distance “a” must be allowed between the control gate
10
and the common source region
16
as shown in FIG.
2
B.
In general, this type of flash memory structure has several defects. Firstly, the field oxide insulation structure will produce a rounded corner structure
19
in the common source region
16
close to the control gate
10
when viewed from above (as shown in FIG.
1
). Secondly, the field oxide layer in this region has a lateral extension known commonly as the bird's beak as shown in FIG.
2
B. Therefore, extra space “a” (as shown in
FIG. 1
) between the control gate
10
and the common source region
16
must be set aside to prevent unwanted leakage current and short-circuiting.
In general, most integrated circuits must have some form of insulation for isolating one device from its close neighbors. Field oxide layers used to be one of the most commonly used isolating structure. However, the field oxide layer is gradually being replaced by shallow trench isolation (STI) structures. At present, most flash memory structure uses shallow trench isolation. This is because STI has better structural properties than conventional field oxide structure, and furthermore can save chip area. Normally, shallow trench isolation is formed by first performing an anisotropic dry etching operation to form a trench in a substrate, and then depositing some oxide material into the trench.
However, when shallow trench isolation is applied to the fabrication of flash memory structure, area occupied by each device is still large. Moreover, if the common source region and the gate structure are too close together, and the gate oxide layer is too thin, problems such as leakage current or unwanted short-circuiting still have to be dealt with.
In light of the foregoing, there is a need to improve the flash memory structure and method of manufacture.
SUMMARY OF THE INVENTION
Accordingly, the present invention provides a flash memory structure and its method of manufacture. The structure includes a buried metal layer that can save device area and is capable of providing higher density for a device array. Moreover, processing steps necessary for forming the structure are simple, and a shallow trench isolation structure can be easily manufactured as well. In addition, the common source also has a flatter cross section and a better alignment.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a method of manufacturing flash memory. The method comprises the steps of first providing a semiconductor substrate, and then forming a shallow trench isolation structure within the substrate. Next, the shallow trench isolation structure is etched to form a shallow trench. The shallow trench is formed in the desired common source regions. Moreover, the shallow trench isolation structure has a greater depth than the shallow trench. Thereafter, metallic material is deposited into the trench, and then the metallic layer is polished to a level roughly the same as the upper surface of the semiconductor substrate. Hence, a buried metallic layer is formed. Subsequently, a polysilicon layer is formed over the substrate, and then the polysilicon layer is patterned. Then, ions are implanted into the substrate on each side of the polysilicon layer using the polysilicon layer as a mask to form a source region and a drain region, respectively. The source region and the buried metallic layer alternately connect with each other to form a common source region. Finally, metallic interconnects are formed above the polysilicon layer.
In another aspect, this invention provides a flash memory structure. The structure comprises a semiconductor substrate, a linear polysilicon layer running across above the semiconductor substrate, a drain region in the substrate on one side of the polysilicon layer, a trench isolation structure above the substrate for insulating devices, a buried metallic layer within the substrate such that the buried metallic layer overlaps with a portion of the trench isolation structure, and a common source region within the substrate located on the other side of the polysilicon layer just opposite the drain region such that the common source region is made up of at least a source region and a buried metallic layer connected together.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 5523249 (1996-06-01), Gill et al.
patent: 5547884 (1996-08-01), Yamaguchi et al.
patent: 5553018 (1996-09-01), Wang et al.
patent: 5652447 (1997-07-01), Chen et al.
patent: 5962890 (1999-10-01), Sato
Crane Sara
Huang Jiawei
J.C. Patents
Tran Thien F.
United Microelectronics Corp.
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