Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-01-22
2001-04-10
Lee, Eddie C. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S314000, C257S315000, C257S316000
Reexamination Certificate
active
06215147
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 87113258, filed Aug. 12, 1998, the full disclosure of which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention:
This invention relates to semiconductor fabrication technology, and more particularly, to a flash memory structure with buried bit lines and a method of fabricating the same.
2. Description of Related Art:
Flash memory is a type of erasable and programmable read-only memory (EPROM) that can be easily and quickly reprogrammed. In a flash memory device, each memory cell is formed with a two-layer gate structure (called stacked gate) including a floating gate and a control gate. The floating gate is typically formed from polysilicon and is so named because it is not physically connected to any other conductive structures in the integrated circuit. Whether or not data is stored on a memory cell is dependent on whether or not the floating gate of the memory cell is charged. The control gate is formed over the floating gate and connected to a word line to control the access to the memory cell.
FIG. 1
is a schematic diagram showing the circuit layout of an array of flash memory cells (one of which is enclosed in a dashed circle indicated by the reference numeral
10
). These flash memory cells can be accessed via a plurality of word lines WL
1
, WL
2
and a plurality of bit lines BL
1
, BL
2
, BL
3
that are interconnected in a predetermined manner to the flash memory device. The access operation for each flash memory cell (i.e., read/write operation) is performed through a phenomenon called Fowler-Nordheim tunneling (F-N tunneling) between the floating gates and the associated impurity-doped regions. The access speed is dependent on the mobility of electrons between the floating gates and the impurity-doped regions. The access operation is basic knowledge to those skilled in the art of semiconductor memory devices, so description thereof will not be further detailed.
It is a trend in semiconductor industry to fabricate integrated circuits with high integration. To meet this requirement, the present layout design for the flash memory should be miniaturized in size. However, the achievable level of miniaturization is limited by the present design rule. The fabrication of buried bit lines in a miniaturized, conventional flash memory device would be complex and thus difficult to carry out.
SUMMARY OF THE INVENTION
It is therefore an objective of the present invention to provide a flash memory structure with buried bit lines that are lower in resistance and shallower in buried depth in the substrate than the prior art due to the forming of shallow N
+
junctions.
It is another objective of the present invention to provide a flash memory structure with buried bit lines that are formed with a shallow N
+
junction having a smaller contact area with the substrate so that the punchthrough margin can be increased to allow enhanced reliability to the flash memory device.
In accordance with the foregoing and other objectives of the present invention, an improved flash memory structure and a method of fabricating the same are provided.
The flash memory structure includes a semiconductor substrate; a tunneling oxide layer formed over the substrate; a plurality of floating gates formed at predefined locations over the tunneling oxide layer; a plurality of sidewall spacers, each formed on the sidewall of one of the floating gates; a plurality of selective polysilicon blocks, each formed between one neighboring pair of the floating gates; a plurality of impurity-doped regions in the substrate, each formed beneath one of the selective polysilicon blocks to serve as a plurality of buried bit line for the flash memory device; a plurality of insulating layers, each formed over one of the selective polysilicon blocks; a dielectric layer covering all of the floating gates and the insulating layers; and a plurality of control gates formed over the dielectric layer, each located above one of the floating gates.
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patent: 6037221 (2000-03-01), Lee et al.
patent: 000573169 (1994-06-01), None
patent: 406163921 (1994-06-01), None
Huang Jiawei
Lee Eddie C.
Ortiz Edgardo
Patents J. C.
United Microelectronics Corp.
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