Flash memory programming power reduction

Static information storage and retrieval – Read/write circuit – Including reference or bias voltage generator

Reexamination Certificate

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Details

C365S185110, C365S185180, C365S189110, C365S202000, C365S230030

Reexamination Certificate

active

07957204

ABSTRACT:
A non-volatile memory device includes an array of non-volatile memory cells. When programming the memory cells, a voltage supply source is used that includes multiple independent charge pumps. The independent charge pumps supply the programming voltage to different ones of bit lines in the array of memory cells. Using multiple charge pumps tends to reduce output voltage fluctuations and thereby reduce power loss.

REFERENCES:
patent: 5291446 (1994-03-01), Van Buskirk et al.
patent: 5301097 (1994-04-01), McDaniel
patent: 5430674 (1995-07-01), Javanifard
patent: 5444655 (1995-08-01), Yoshikawa
patent: 5473573 (1995-12-01), Rao
patent: 5539688 (1996-07-01), Yiu et al.
patent: 5638326 (1997-06-01), Hollmer et al.
patent: 5751637 (1998-05-01), Chen et al.
patent: 5787039 (1998-07-01), Chen et al.
patent: 5890192 (1999-03-01), Lee et al.
patent: 5892710 (1999-04-01), Fazio et al.
patent: 6044022 (2000-03-01), Nachumovsky
patent: 6101125 (2000-08-01), Gorman
patent: 6233177 (2001-05-01), Shokouhi et al.
patent: 6272670 (2001-08-01), Van Myers et al.
patent: 6295228 (2001-09-01), Pawletko et al.
patent: 6327181 (2001-12-01), Akaogi et al.
patent: 6424570 (2002-07-01), Le et al.
patent: 6426893 (2002-07-01), Conley et al.
patent: 6452869 (2002-09-01), Parker
patent: 6487121 (2002-11-01), Thurgate et al.
patent: 6496410 (2002-12-01), Parker
patent: 6535419 (2003-03-01), Parker et al.
patent: 6538923 (2003-03-01), Parker
patent: 6570785 (2003-05-01), Mangan et al.
patent: 6724662 (2004-04-01), Manea
patent: 6747900 (2004-06-01), Park et al.
patent: 6775187 (2004-08-01), Hamilton et al.
patent: 6816001 (2004-11-01), Khouri et al.
patent: 6952366 (2005-10-01), Forbes
patent: 6996021 (2006-02-01), Derner et al.
patent: 7020018 (2006-03-01), Hsieh et al.
patent: 7149110 (2006-12-01), Tran et al.
patent: 7151701 (2006-12-01), Combe et al.
patent: 7177184 (2007-02-01), Chen
patent: 7190616 (2007-03-01), Forbes et al.
patent: 2001/0040836 (2001-11-01), Mori et al.
patent: 2002/0167844 (2002-11-01), Han et al.
patent: 2003/0093233 (2003-05-01), Rajguru
patent: 2003/0142544 (2003-07-01), Maayan et al.
patent: 2003/0172309 (2003-09-01), Cioaca
patent: 2004/0027857 (2004-02-01), Ooishi
patent: 2004/0037113 (2004-02-01), Ooishi
patent: WO 03/063167 (2003-07-01), None
patent: WO 2005/106891 (2005-11-01), None
Co-pending U.S. Appl. No. 11/212,614, filed Aug. 29, 2005, entitled: “Voltage Regulator with Less Overshoot and Faster Settling Time,” Yonggang Wu et al.; 30 pp.
Co-pending U.S. Appl. No. 11/229,664, filed Sep. 20, 2005, entitled: “Flash Memory Programming Using an Indication Bit to Interpret State,” Takao Akaogi et al.; 25 pp.
International Search Report and Written Opinion dated Jan. 15, 2007.
2002 IEEE International Solid State Circuits Conference, Session 6, “SRAM and Non-Volatile Memories,” Feb. 4, 2004, 6 pages.
2002 IEEE International Solid State Circuits Conference, 23 pages.

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